[PATCH] D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:233
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  assert(hasSEW(TSFlags) && "The instruction doesn't have SEW value!");
+  if (hasSEWOp(TSFlags))
----------------
I think this patch creates a scenario where `!hasSEW(TSFlags) && pseudoNameContainsSEW(Opcode)`. This patch removes SEW operand from loads and stores that have SEW in the pseudo name. These instructions still have SEW information in them that we are not extracting in this function, since this creates the case `!hasSEW(TSFlags)` for these loads and stores.

Obviously we cannot return `MachineOperand` when SEW is a part of the Opcode name and not an operand. However, in the places that `getSEWOp` wants the `MachineOperand` just for the immediate value, then we should be able to say what that immediate is with `getLog2SEW` that either gets it from TSFlags or from Opcode (if it exists as a part of either).

I think the issue of missing opportunities to report SEW, in the case that it is only part of the opcode and not an operand also applies to `getLog2SEW`.



Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159368/new/

https://reviews.llvm.org/D159368