[llvm] [RISCV][MC] Implement evaluateBranch for auipc+jalr pairs (PR #65480)
Job Noorman via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 6 08:12:52 PDT 2023
https://github.com/mtvec updated https://github.com/llvm/llvm-project/pull/65480:
>From 72286701c48d722a7fbb43b4e1ca36b4f99ef2e1 Mon Sep 17 00:00:00 2001
From: Job Noorman <jnoorman at igalia.com>
Date: Wed, 6 Sep 2023 11:29:28 +0200
Subject: [PATCH 1/2] [MC][NFC] Allow MCInstrAnalysis to store state
Currently, all the analysis functions provided by `MCInstrAnalysis` work
on a single instruction. On some targets, this limits the kind of
instructions that can be successfully analyzed as common constructs may
need multiple instructions.
For example, a typical call sequence on RISC-V uses a auipc+jalr pair.
In order to analyse the jalr inside `evaluateBranch`, information about
the corresponding auipc is needed. Similarly, AArch64 uses adrp+ldr
pairs to access globals.
This patch proposes to add state to `MCInstrAnalysis` to support these
use cases. Two new virtual methods are added:
- `updateState`: takes an instruction and its address. This methods
should be called by clients on every instruction and allows targets to
store whatever information they need to analyse future instructions.
- `resetState`: clears the state whenever it becomes irrelevant. Clients
could call this, for example, when starting to disassemble a new
function.
Note that the default implementations do nothing so this patch is NFC.
No actual state is stored inside `MCInstrAnalysis`; deciding the
structure of the state is left to the targets.
This patch also modifies llvm-objdump to use the new interface.
This patch is an alternative to D116677 and the idea of storing state in
`MCInstrAnalysis` was first discussed there.
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 15 +++++++++++++++
llvm/tools/llvm-objdump/llvm-objdump.cpp | 21 ++++++++++++++++-----
2 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index c3c675c39c5590c..dac12af599e6f34 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -37,6 +37,21 @@ class MCInstrAnalysis {
MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
virtual ~MCInstrAnalysis() = default;
+ /// Clear the internal state. See updateState for more information.
+ virtual void resetState() {}
+
+ /// Update internal state with \p Inst at \p Addr.
+ ///
+ /// For some types a analyses, inspecting a single instruction is not
+ /// sufficient. Some examples are auipc/jalr pairs on RISC-V or adrp/ldr pairs
+ /// on AArch64. To support inspecting multiple instructions, targets may keep
+ /// track of an internal state while analysing instructions. Clients should
+ /// call updateState for every instruction which allows later calls to one of
+ /// the analysis functions to take previous instructions into account.
+ /// Whenever state becomes irrelevant (e.g., when starting to disassemble a
+ /// new function), clients should call resetState to clear it.
+ virtual void updateState(const MCInst &Inst, uint64_t Addr) {}
+
virtual bool isBranch(const MCInst &Inst) const {
return Info->get(Inst.getOpcode()).isBranch();
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 96d74d6e2d5e865..8f6479d3c6e31e4 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -842,7 +842,7 @@ class DisassemblerTarget {
std::unique_ptr<const MCSubtargetInfo> SubtargetInfo;
std::shared_ptr<MCContext> Context;
std::unique_ptr<MCDisassembler> DisAsm;
- std::shared_ptr<const MCInstrAnalysis> InstrAnalysis;
+ std::shared_ptr<MCInstrAnalysis> InstrAnalysis;
std::shared_ptr<MCInstPrinter> InstPrinter;
PrettyPrinter *Printer;
@@ -1265,14 +1265,19 @@ collectBBAddrMapLabels(const std::unordered_map<uint64_t, BBAddrMap> &AddrToBBAd
}
}
-static void collectLocalBranchTargets(
- ArrayRef<uint8_t> Bytes, const MCInstrAnalysis *MIA, MCDisassembler *DisAsm,
- MCInstPrinter *IP, const MCSubtargetInfo *STI, uint64_t SectionAddr,
- uint64_t Start, uint64_t End, std::unordered_map<uint64_t, std::string> &Labels) {
+static void
+collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
+ MCDisassembler *DisAsm, MCInstPrinter *IP,
+ const MCSubtargetInfo *STI, uint64_t SectionAddr,
+ uint64_t Start, uint64_t End,
+ std::unordered_map<uint64_t, std::string> &Labels) {
// So far only supports PowerPC and X86.
if (!STI->getTargetTriple().isPPC() && !STI->getTargetTriple().isX86())
return;
+ if (MIA)
+ MIA->resetState();
+
Labels.clear();
unsigned LabelCount = 0;
Start += SectionAddr;
@@ -1298,6 +1303,7 @@ static void collectLocalBranchTargets(
!Labels.count(Target) &&
!(STI->getTargetTriple().isPPC() && Target == Index))
Labels[Target] = ("L" + Twine(LabelCount++)).str();
+ MIA->updateState(Inst, Index);
}
Index += Size;
}
@@ -1939,6 +1945,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
BBAddrMapLabels);
}
+ if (DT->InstrAnalysis)
+ DT->InstrAnalysis->resetState();
+
while (Index < End) {
// ARM and AArch64 ELF binaries can interleave data and text in the
// same section. We rely on the markers introduced to understand what
@@ -2155,6 +2164,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (TargetOS == &CommentStream)
*TargetOS << "\n";
}
+
+ DT->InstrAnalysis->updateState(Inst, SectionAddr + Index);
}
}
>From 2b9d08907bcf8c2fb16b2f35f39b68824b35bd1e Mon Sep 17 00:00:00 2001
From: Job Noorman <jnoorman at igalia.com>
Date: Wed, 6 Sep 2023 11:29:28 +0200
Subject: [PATCH 2/2] [RISCV][MC] Implement evaluateBranch for auipc+jalr pairs
This patch implements `MCInstrAnalysis` state in order to be able
analyze auipc+jalr pairs inside `evaluateBranch`.
This is implemented as follows:
- State: array of currently known GPR values;
- Whenever an auipc is detected in `updateState`, update the state value
of RD with the immediate;
- Whenever a jalr is detected in `evaluateBranch`, check if the state
holds a value for RS1 and use that to compute its target.
Note that this is similar to how binutils implements it and the output
of llvm-objdump should now mostly match the one of GNU objdump.
This patch also updates the relevant llvm-objdump patches and adds a new
one testing the output for interleaved auipc+jalr pairs.
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 39 +++++++++++++++++++
.../tools/llvm-objdump/ELF/RISCV/branches.s | 4 +-
.../ELF/RISCV/multi-instr-target.s | 18 +++++++++
3 files changed, 59 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 75af5c2de09469b..848f5b7e6d66fea 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -114,10 +114,40 @@ static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
+ std::optional<int64_t> GPRState[31];
+
+ void setGPRState(unsigned Reg, int64_t Value) {
+ assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+ if (Reg != RISCV::X0)
+ GPRState[Reg - RISCV::X1] = Value;
+ }
+
+ std::optional<int64_t> getGPRState(unsigned Reg) const {
+ assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+ if (Reg == RISCV::X0)
+ return 0;
+ return GPRState[Reg - RISCV::X1];
+ }
+
public:
explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
: MCInstrAnalysis(Info) {}
+ void resetState() override {
+ std::fill(std::begin(GPRState), std::end(GPRState), std::nullopt);
+ }
+
+ void updateState(const MCInst &Inst, uint64_t Addr) override {
+ switch (Inst.getOpcode()) {
+ case RISCV::AUIPC:
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + (Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ }
+
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const override {
if (isConditionalBranch(Inst)) {
@@ -140,6 +170,15 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
return true;
}
+ if (Inst.getOpcode() == RISCV::JALR) {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
+ }
+
+ return false;
+ }
+
return false;
}
diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
index 5fec4e6e25a39a3..ebd86a702b70e7c 100644
--- a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
@@ -57,11 +57,11 @@ c.jal bar
c.j bar
# CHECK: auipc ra, 0
-# CHECK: jalr ra, 16(ra){{$}}
+# CHECK: jalr ra, 16(ra) <foo+0x58>
call .Llocal
# CHECK: auipc ra, 0
-# CHECK: jalr ra, 16(ra){{$}}
+# CHECK: jalr ra, 16(ra) <bar>
call bar
.Llocal:
diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s
new file mode 100644
index 000000000000000..c1a05032e261857
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s | \
+# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn - | \
+# RUN: FileCheck %s
+
+## Test multiple interleaved auipc/jalr pairs
+# CHECK: auipc t0, 0
+1: auipc t0, %pcrel_hi(bar)
+# CHECK: auipc t1, 0
+2: auipc t1, %pcrel_hi(bar)
+# CHECK: jalr ra, 16(t0) <bar>
+jalr %pcrel_lo(1b)(t0)
+# CHECK: jalr ra, 12(t1) <bar>
+jalr %pcrel_lo(2b)(t1)
+
+# CHECK-LABEL: <bar>:
+bar:
+# CHECK: c.nop
+nop
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