[PATCH] D159053: [RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:5509
+      // Skip constant.
+      if (auto Const = dyn_cast<ConstantSDNode>(Scalar))
+        break;
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michaelmaitland wrote:
> craig.topper wrote:
> > This seems like it might be a RISC-V specific issue and not something we should do in target specific code.
> > 
> > What code is reversing the promotion? That code should be checking isOperationLegal
> If you end up doing this check, either here on in RISCV specific code, you can simplify to `if (isa<ConstantSDNode>(Scalar))`
Thanks for your advice, I use implement it in RISCV target specific logic now.


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  https://reviews.llvm.org/D159053/new/

https://reviews.llvm.org/D159053