[llvm] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)
Mark de Wever via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 5 09:44:16 PDT 2023
https://github.com/mordante updated https://github.com/llvm/llvm-project/pull/65283:
>From b9f24033f7f2d3485fbabbc56e3b31b5bc90e874 Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq at xs4all.nl>
Date: Sun, 20 Aug 2023 12:30:57 +0200
Subject: [PATCH 01/10] [libc++][C++20 modules] Enabling in C++20.
The vendors of the MSVC STL, libstdc++ and libc++ have agreed [1] to
make the C++23 modules std and std.compat available in C++20. This
provides the std module; libc++ has not implemented the std.compat
module yet.
[1] https://github.com/microsoft/STL/issues/3945
Depends on D158357
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D158358
---
libcxx/docs/Modules.rst | 3 +++
libcxx/docs/UsingLibcxx.rst | 6 ++++++
libcxx/modules/std/algorithm.inc | 8 +++++---
libcxx/modules/std/bit.inc | 2 ++
libcxx/modules/std/expected.inc | 2 ++
libcxx/modules/std/format.inc | 4 ++++
libcxx/modules/std/functional.inc | 2 ++
libcxx/modules/std/mdspan.inc | 2 ++
libcxx/modules/std/memory.inc | 2 ++
libcxx/modules/std/print.inc | 6 ++++--
libcxx/modules/std/ranges.inc | 10 ++++++++++
libcxx/modules/std/string.inc | 2 +-
libcxx/modules/std/thread.inc | 2 ++
libcxx/modules/std/tuple.inc | 2 ++
libcxx/modules/std/type_traits.inc | 4 ++++
libcxx/modules/std/utility.inc | 6 ++++++
libcxx/modules/std/vector.inc | 2 ++
libcxx/test/libcxx/module_std.gen.py | 2 +-
libcxx/test/lit.local.cfg | 2 ++
libcxx/utils/ci/buildkite-pipeline.yml | 8 ++++++--
20 files changed, 68 insertions(+), 9 deletions(-)
diff --git a/libcxx/docs/Modules.rst b/libcxx/docs/Modules.rst
index f7c4ea9412baadf..85c42af5a62b8db 100644
--- a/libcxx/docs/Modules.rst
+++ b/libcxx/docs/Modules.rst
@@ -49,10 +49,13 @@ What works
* ``LIBCXX_ENABLE_RANDOM_DEVICE``
* ``LIBCXX_ENABLE_UNICODE``
+ * A C++20 based extension
+
Some of the current limitations
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* There is no official build system support, libc++ has experimental CMake support
+ * Requires CMake 3.26 for C++20 support
* Requires CMake 3.26 for C++23 support
* Requires CMake 3.27 for C++26 support
* Requires Ninja 1.11
diff --git a/libcxx/docs/UsingLibcxx.rst b/libcxx/docs/UsingLibcxx.rst
index 1859645320a4056..71a934f4bf28726 100644
--- a/libcxx/docs/UsingLibcxx.rst
+++ b/libcxx/docs/UsingLibcxx.rst
@@ -520,6 +520,12 @@ in their code base.
In C++26 formatting pointers gained a type ``P`` and allows to use
zero-padding. These options have been retroactively applied to C++20.
+Extensions to the C++23 modules ``std`` and ``std.compat``
+----------------------------------------------------------
+
+Like other major implementations, libc++ provides C++23 modules ``std`` and
+``std.compat`` in C++20 as an extension"
+
.. _turning-off-asan:
Turning off ASan annotation in containers
diff --git a/libcxx/modules/std/algorithm.inc b/libcxx/modules/std/algorithm.inc
index bb38f39df888961..c951b2b36c82739 100644
--- a/libcxx/modules/std/algorithm.inc
+++ b/libcxx/modules/std/algorithm.inc
@@ -150,10 +150,11 @@ export namespace std {
}
namespace ranges {
+#if _LIBCPP_STD_VER >= 23
// [alg.starts.with], starts with
using std::ranges::starts_with;
-#if 0
+# if 0
// [alg.ends.with], ends with
using std::ranges::ends_with;
@@ -167,8 +168,9 @@ export namespace std {
using std::ranges::fold_left_with_iter;
using std::ranges::fold_left_first_with_iter;
using std::ranges::fold_left_first_with_iter;
-#endif
- } // namespace ranges
+# endif
+#endif // _LIBCPP_STD_VER >= 23
+ } // namespace ranges
// [alg.modifying.operations], mutating sequence operations
// [alg.copy], copy
diff --git a/libcxx/modules/std/bit.inc b/libcxx/modules/std/bit.inc
index 2a05a8ee46dc4b7..027a6c17ad6a6b0 100644
--- a/libcxx/modules/std/bit.inc
+++ b/libcxx/modules/std/bit.inc
@@ -11,8 +11,10 @@ export namespace std {
// [bit.cast], bit_cast
using std::bit_cast;
+#if _LIBCPP_STD_VER >= 23
// [bit.byteswap], byteswap
using std::byteswap;
+#endif
// [bit.pow.two], integral powers of 2
using std::bit_ceil;
diff --git a/libcxx/modules/std/expected.inc b/libcxx/modules/std/expected.inc
index 1595230123dea89..c21683cb90d6348 100644
--- a/libcxx/modules/std/expected.inc
+++ b/libcxx/modules/std/expected.inc
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
export namespace std {
+#if _LIBCPP_STD_VER >= 23
// [expected.unexpected], class template unexpected
using std::unexpected;
@@ -20,4 +21,5 @@ export namespace std {
// [expected.expected], class template expected
using std::expected;
+#endif // _LIBCPP_STD_VER >= 23
} // namespace std
diff --git a/libcxx/modules/std/format.inc b/libcxx/modules/std/format.inc
index ae7de95495cf8c5..c1bc91f8317dd0a 100644
--- a/libcxx/modules/std/format.inc
+++ b/libcxx/modules/std/format.inc
@@ -42,8 +42,10 @@ export namespace std {
// [format.formatter], formatter
using std::formatter;
+#if _LIBCPP_STD_VER >= 23
// [format.formattable], concept formattable
using std::formattable;
+#endif
// [format.parse.ctx], class template basic_format_parse_context
using std::basic_format_parse_context;
@@ -52,6 +54,7 @@ export namespace std {
using std::wformat_parse_context;
#endif
+#if _LIBCPP_STD_VER >= 23
// [format.range], formatting of ranges
// [format.range.fmtkind], variable template format_kind
using std::format_kind;
@@ -59,6 +62,7 @@ export namespace std {
// [format.range.formatter], class template range_formatter
using std::range_formatter;
+#endif // _LIBCPP_STD_VER >= 23
// [format.arg], class template basic_format_arg
using std::basic_format_arg;
diff --git a/libcxx/modules/std/functional.inc b/libcxx/modules/std/functional.inc
index f8a29e2f058f8f2..1148944a9d2fee3 100644
--- a/libcxx/modules/std/functional.inc
+++ b/libcxx/modules/std/functional.inc
@@ -10,7 +10,9 @@
export namespace std {
// [func.invoke], invoke
using std::invoke;
+#if _LIBCPP_STD_VER >= 23
using std::invoke_r;
+#endif
// [refwrap], reference_wrapper
using std::reference_wrapper;
diff --git a/libcxx/modules/std/mdspan.inc b/libcxx/modules/std/mdspan.inc
index 37580eaa458b41b..888c94ad59cfd9a 100644
--- a/libcxx/modules/std/mdspan.inc
+++ b/libcxx/modules/std/mdspan.inc
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
export namespace std {
+#if _LIBCPP_STD_VER >= 23
// [mdspan.extents], class template extents
using std::extents;
@@ -24,4 +25,5 @@ export namespace std {
// [mdspan.mdspan], class template mdspan
using std::mdspan;
+#endif // _LIBCPP_STD_VER >= 23
} // namespace std
diff --git a/libcxx/modules/std/memory.inc b/libcxx/modules/std/memory.inc
index d91c549e854f90c..fba2461732c1b9d 100644
--- a/libcxx/modules/std/memory.inc
+++ b/libcxx/modules/std/memory.inc
@@ -41,9 +41,11 @@ export namespace std {
// [allocator.traits], allocator traits
using std::allocator_traits;
+#if _LIBCPP_STD_VER >= 23
using std::allocation_result;
using std::allocate_at_least;
+#endif
// [default.allocator], the default allocator
using std::allocator;
diff --git a/libcxx/modules/std/print.inc b/libcxx/modules/std/print.inc
index 35a1635cf201f39..1ca52c700688721 100644
--- a/libcxx/modules/std/print.inc
+++ b/libcxx/modules/std/print.inc
@@ -8,12 +8,14 @@
//===----------------------------------------------------------------------===//
export namespace std {
+#if _LIBCPP_STD_VER >= 23
// [print.fun], print functions
using std::print;
using std::println;
using std::vprint_nonunicode;
-#ifndef _LIBCPP_HAS_NO_UNICODE
+# ifndef _LIBCPP_HAS_NO_UNICODE
using std::vprint_unicode;
-#endif // _LIBCPP_HAS_NO_UNICODE
+# endif // _LIBCPP_HAS_NO_UNICODE
+#endif // _LIBCPP_STD_VER >= 23
} // namespace std
diff --git a/libcxx/modules/std/ranges.inc b/libcxx/modules/std/ranges.inc
index a6b1bf5496251a8..67b0f02ad9d980f 100644
--- a/libcxx/modules/std/ranges.inc
+++ b/libcxx/modules/std/ranges.inc
@@ -90,8 +90,10 @@ export namespace std {
using std::ranges::borrowed_subrange_t;
+#if _LIBCPP_STD_VER >= 23
// [range.utility.conv], range conversions
using std::ranges::to;
+#endif
// [range.empty], empty view
using std::ranges::empty_view;
@@ -114,12 +116,14 @@ export namespace std {
using std::ranges::views::iota;
} // namespace views
+#if _LIBCPP_STD_VER >= 23
// [range.repeat], repeat view
using std::ranges::repeat_view;
namespace views {
using std::ranges::views::repeat;
} // namespace views
+#endif // _LIBCPP_STD_VER >= 23
#ifndef _LIBCPP_HAS_NO_LOCALIZATION
// [range.istream], istream view
@@ -149,12 +153,14 @@ export namespace std {
// [range.owning.view], owning view
using std::ranges::owning_view;
+#if _LIBCPP_STD_VER >= 23
// [range.as.rvalue], as rvalue view
using std::ranges::as_rvalue_view;
namespace views {
using std::ranges::views::as_rvalue;
} // namespace views
+#endif // _LIBCPP_STD_VER >= 23
// [range.filter], filter view
using std::ranges::filter_view;
@@ -259,12 +265,14 @@ export namespace std {
using std::ranges::views::values;
} // namespace views
+#if _LIBCPP_STD_VER >= 23
// [range.zip], zip view
using std::ranges::zip_view;
namespace views {
using std::ranges::views::zip;
} // namespace views
+#endif // _LIBCPP_STD_VER >= 23
#if 0
// [range.zip.transform], zip transform view
@@ -329,6 +337,8 @@ export namespace std {
using std::tuple_element;
using std::tuple_size;
+#if _LIBCPP_STD_VER >= 23
using std::from_range;
using std::from_range_t;
+#endif // _LIBCPP_STD_VER >= 23
} // namespace std
diff --git a/libcxx/modules/std/string.inc b/libcxx/modules/std/string.inc
index 76b384c8b54be48..8366690fd9d37d0 100644
--- a/libcxx/modules/std/string.inc
+++ b/libcxx/modules/std/string.inc
@@ -68,7 +68,7 @@ export namespace std {
using std::hash;
// TODO MODULES is this a bug?
-#if 1
+#if _LIBCPP_STD_VER >= 23
using std::operator""s;
#else
inline namespace literals {
diff --git a/libcxx/modules/std/thread.inc b/libcxx/modules/std/thread.inc
index 114840e3d1cbf9f..43594d1a29cf305 100644
--- a/libcxx/modules/std/thread.inc
+++ b/libcxx/modules/std/thread.inc
@@ -33,7 +33,9 @@ export namespace std {
using std::operator<<;
# endif // _LIBCPP_HAS_NO_LOCALIZATION
+# if _LIBCPP_STD_VER >= 23
using std::formatter;
+# endif
using std::hash;
#endif // _LIBCPP_HAS_NO_THREADS
diff --git a/libcxx/modules/std/tuple.inc b/libcxx/modules/std/tuple.inc
index 9a8fb72cb63ea53..706e2266c174b77 100644
--- a/libcxx/modules/std/tuple.inc
+++ b/libcxx/modules/std/tuple.inc
@@ -13,9 +13,11 @@ export namespace std {
// [tuple.like], concept tuple-like
+#if _LIBCPP_STD_VER >= 23
// [tuple.common.ref], common_reference related specializations
using std::basic_common_reference;
using std::common_type;
+#endif
// [tuple.creation], tuple creation functions
using std::ignore;
diff --git a/libcxx/modules/std/type_traits.inc b/libcxx/modules/std/type_traits.inc
index f0ec4cb6c71a301..d368daf35ccb8c0 100644
--- a/libcxx/modules/std/type_traits.inc
+++ b/libcxx/modules/std/type_traits.inc
@@ -53,7 +53,9 @@ export namespace std {
using std::is_volatile;
using std::is_bounded_array;
+#if _LIBCPP_STD_VER >= 23
using std::is_scoped_enum;
+#endif
using std::is_signed;
using std::is_unbounded_array;
using std::is_unsigned;
@@ -255,7 +257,9 @@ export namespace std {
using std::is_nothrow_swappable_v;
using std::is_nothrow_swappable_with_v;
using std::is_polymorphic_v;
+#if _LIBCPP_STD_VER >= 23
using std::is_scoped_enum_v;
+#endif
using std::is_signed_v;
using std::is_standard_layout_v;
using std::is_swappable_v;
diff --git a/libcxx/modules/std/utility.inc b/libcxx/modules/std/utility.inc
index c8e4dc396cff3e9..77c21b87640dd46 100644
--- a/libcxx/modules/std/utility.inc
+++ b/libcxx/modules/std/utility.inc
@@ -16,7 +16,9 @@ export namespace std {
// [forward], forward/move
using std::forward;
+#if _LIBCPP_STD_VER >= 23
using std::forward_like;
+#endif
using std::move;
using std::move_if_noexcept;
@@ -37,11 +39,13 @@ export namespace std {
using std::in_range;
+#if _LIBCPP_STD_VER >= 23
// [utility.underlying], to_underlying
using std::to_underlying;
// [utility.unreachable], unreachable
using std::unreachable;
+#endif // _LIBCPP_STD_VER >= 23
// [intseq], compile-time integer sequences
using std::index_sequence;
@@ -55,8 +59,10 @@ export namespace std {
// [pairs], class template pair
using std::pair;
+#if _LIBCPP_STD_VER >= 23
using std::basic_common_reference;
using std::common_type;
+#endif
// [pairs.spec], pair specialized algorithms
using std::operator==;
using std::operator<=>;
diff --git a/libcxx/modules/std/vector.inc b/libcxx/modules/std/vector.inc
index a9ce764fc81da88..7168ec2bb703572 100644
--- a/libcxx/modules/std/vector.inc
+++ b/libcxx/modules/std/vector.inc
@@ -27,6 +27,8 @@ export namespace std {
// hash support
using std::hash;
+#if _LIBCPP_STD_VER >= 23
// [vector.bool.fmt], formatter specialization for vector<bool>
using std::formatter;
+#endif
} // namespace std
diff --git a/libcxx/test/libcxx/module_std.gen.py b/libcxx/test/libcxx/module_std.gen.py
index 2a6b0f237afc7d3..8bd4f702c7fc9b7 100644
--- a/libcxx/test/libcxx/module_std.gen.py
+++ b/libcxx/test/libcxx/module_std.gen.py
@@ -117,7 +117,7 @@
print(
f"""\
//--- module_std.sh.cpp
-// UNSUPPORTED{BLOCKLIT}: c++03, c++11, c++14, c++17, c++20
+// UNSUPPORTED{BLOCKLIT}: c++03, c++11, c++14, c++17
// UNSUPPORTED{BLOCKLIT}: libcpp-has-no-std-modules
// UNSUPPORTED{BLOCKLIT}: modules-build
diff --git a/libcxx/test/lit.local.cfg b/libcxx/test/lit.local.cfg
index 16ab3b1b622a1c0..ede8c65d89a0ba6 100644
--- a/libcxx/test/lit.local.cfg
+++ b/libcxx/test/lit.local.cfg
@@ -34,6 +34,8 @@ if std == "cxx26":
std = "26"
elif std == "cxx23":
std = "23"
+elif std == "cxx20":
+ std = "20"
else:
std = ""
diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml
index 723ae438619745f..5c1010e81a9c5c9 100644
--- a/libcxx/utils/ci/buildkite-pipeline.yml
+++ b/libcxx/utils/ci/buildkite-pipeline.yml
@@ -218,9 +218,13 @@ steps:
- "**/test-results.xml"
- "**/*.abilist"
env:
- CC: "clang-${LLVM_HEAD_VERSION}"
- CXX: "clang++-${LLVM_HEAD_VERSION}"
+ # Note: Modules require and absolute path for clang-scan-deps
+ # https://github.com/llvm/llvm-project/issues/61006
+ CC: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang"
+ CXX: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang++"
+ CMAKE: "/opt/bin/cmake"
ENABLE_CLANG_TIDY: "On"
+ ENABLE_STD_MODULES: "On"
agents:
queue: "libcxx-builders"
os: "linux"
>From 18a628ec4ef72bcc005e2e9d5757445c31c6e2f8 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 8 Jul 2023 22:42:36 +0300
Subject: [PATCH 02/10] [AST] Use correct APSInt width when evaluating string
literals
The width of the APSInt values should be the width of an element.
getCharByteWidth returns the size of an element in _host_ bytes, which
makes the width N times greater, where N is the ratio between target's
CHAR_BIT and host's CHAR_BIT.
This is NFC for in-tree targets because all of them have CHAR_BIT == 8.
Reviewed By: cor3ntin, aaron.ballman
Differential Revision: https://reviews.llvm.org/D154773
---
clang/lib/AST/ExprConstant.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 0f37bcf0d5c8524..d8632f53bb1eef4 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -3463,8 +3463,7 @@ static APSInt extractStringLiteralCharacter(EvalInfo &Info, const Expr *Lit,
assert(CAT && "string literal isn't an array");
QualType CharType = CAT->getElementType();
assert(CharType->isIntegerType() && "unexpected character type");
-
- APSInt Value(S->getCharByteWidth() * Info.Ctx.getCharWidth(),
+ APSInt Value(Info.Ctx.getTypeSize(CharType),
CharType->isUnsignedIntegerType());
if (Index < S->getLength())
Value = S->getCodeUnit(Index);
@@ -3487,7 +3486,7 @@ static void expandStringLiteral(EvalInfo &Info, const StringLiteral *S,
unsigned Elts = CAT->getSize().getZExtValue();
Result = APValue(APValue::UninitArray(),
std::min(S->getLength(), Elts), Elts);
- APSInt Value(S->getCharByteWidth() * Info.Ctx.getCharWidth(),
+ APSInt Value(Info.Ctx.getTypeSize(CharType),
CharType->isUnsignedIntegerType());
if (Result.hasArrayFiller())
Result.getArrayFiller() = APValue(Value);
>From 61dd5398368eaa59e4cf86ee33a9b896b83c4d60 Mon Sep 17 00:00:00 2001
From: Abhinav271828 <71174780+Abhinav271828 at users.noreply.github.com>
Date: Tue, 5 Sep 2023 17:14:57 +0100
Subject: [PATCH 03/10] [MLIR][Presburger] Fraction: implement arithmetic
operations (/, +, -) and printing (#65310)
---
.../mlir/Analysis/Presburger/Fraction.h | 58 +++++++++++++++++--
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/mlir/include/mlir/Analysis/Presburger/Fraction.h b/mlir/include/mlir/Analysis/Presburger/Fraction.h
index c51b6c972bf8851..74127a900d53ed2 100644
--- a/mlir/include/mlir/Analysis/Presburger/Fraction.h
+++ b/mlir/include/mlir/Analysis/Presburger/Fraction.h
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This is a simple class to represent fractions. It supports multiplication,
+// This is a simple class to represent fractions. It supports arithmetic,
// comparison, floor, and ceiling operations.
//
//===----------------------------------------------------------------------===//
@@ -30,15 +30,15 @@ struct Fraction {
Fraction() = default;
/// Construct a Fraction from a numerator and denominator.
- Fraction(const MPInt &oNum, const MPInt &oDen) : num(oNum), den(oDen) {
+ Fraction(const MPInt &oNum, const MPInt &oDen = MPInt(1)) : num(oNum), den(oDen) {
if (den < 0) {
num = -num;
den = -den;
}
}
/// Overloads for passing literals.
- Fraction(const MPInt &num, int64_t den) : Fraction(num, MPInt(den)) {}
- Fraction(int64_t num, const MPInt &den) : Fraction(MPInt(num), den) {}
+ Fraction(const MPInt &num, int64_t den = 1) : Fraction(num, MPInt(den)) {}
+ Fraction(int64_t num, const MPInt &den = MPInt(1)) : Fraction(MPInt(num), den) {}
Fraction(int64_t num, int64_t den) : Fraction(MPInt(num), MPInt(den)) {}
// Return the value of the fraction as an integer. This should only be called
@@ -48,6 +48,10 @@ struct Fraction {
return num / den;
}
+ llvm::raw_ostream &print(llvm::raw_ostream &os) const {
+ return os << "(" << num << "/" << den << ")";
+ }
+
/// The numerator and denominator, respectively. The denominator is always
/// positive.
MPInt num{0}, den{1};
@@ -95,8 +99,52 @@ inline bool operator>=(const Fraction &x, const Fraction &y) {
return compare(x, y) >= 0;
}
+inline Fraction reduce(const Fraction &f) {
+ if (f == Fraction(0))
+ return Fraction(0, 1);
+ MPInt g = gcd(f.num, f.den);
+ return Fraction(f.num / g, f.den / g);
+}
+
inline Fraction operator*(const Fraction &x, const Fraction &y) {
- return Fraction(x.num * y.num, x.den * y.den);
+ return reduce(Fraction(x.num * y.num, x.den * y.den));
+}
+
+inline Fraction operator/(const Fraction &x, const Fraction &y) {
+ return reduce(Fraction(x.num * y.den, x.den * y.num));
+}
+
+inline Fraction operator+(const Fraction &x, const Fraction &y) {
+ return reduce(Fraction(x.num * y.den + x.den * y.num, x.den * y.den));
+}
+
+inline Fraction operator-(const Fraction &x, const Fraction &y) {
+ return reduce(Fraction(x.num * y.den - x.den * y.num, x.den * y.den));
+}
+
+inline Fraction& operator+=(Fraction &x, const Fraction &y) {
+ x = x + y;
+ return x;
+}
+
+inline Fraction& operator-=(Fraction &x, const Fraction &y) {
+ x = x - y;
+ return x;
+}
+
+inline Fraction& operator/=(Fraction &x, const Fraction &y) {
+ x = x / y;
+ return x;
+}
+
+inline Fraction& operator*=(Fraction &x, const Fraction &y) {
+ x = x * y;
+ return x;
+}
+
+inline llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const Fraction &x) {
+ x.print(os);
+ return os;
}
} // namespace presburger
>From 54091d37f28c24fa810adf2914af9299c305dd83 Mon Sep 17 00:00:00 2001
From: Sam McCall <sam.mccall at gmail.com>
Date: Tue, 5 Sep 2023 18:15:06 +0200
Subject: [PATCH 04/10] [AST] Fix nested name specifiers printing as
NamespaceNamespace (#65266)
This happens because we print both the kind of the NNS and the kind of
decl (when it refers to one). These are always the same string.
---
clang/lib/AST/TextNodeDumper.cpp | 5 +++--
clang/test/AST/ast-dump-decl.cpp | 2 +-
.../ast-dump-openmp-begin-declare-variant_namespace_1.cpp | 6 +++---
clang/test/AST/ast-dump-using.cpp | 2 +-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp
index c1a7ab10133d584..5c8600035638b3b 100644
--- a/clang/lib/AST/TextNodeDumper.cpp
+++ b/clang/lib/AST/TextNodeDumper.cpp
@@ -16,6 +16,7 @@
#include "clang/AST/DeclOpenMP.h"
#include "clang/AST/DeclTemplate.h"
#include "clang/AST/LocInfoType.h"
+#include "clang/AST/NestedNameSpecifier.h"
#include "clang/AST/Type.h"
#include "clang/Basic/Module.h"
#include "clang/Basic/SourceManager.h"
@@ -792,11 +793,11 @@ void clang::TextNodeDumper::dumpNestedNameSpecifier(const NestedNameSpecifier *N
OS << " '" << NNS->getAsIdentifier()->getName() << "'";
break;
case NestedNameSpecifier::Namespace:
- OS << " Namespace";
+ OS << " "; // "Namespace" is printed as the decl kind.
dumpBareDeclRef(NNS->getAsNamespace());
break;
case NestedNameSpecifier::NamespaceAlias:
- OS << " NamespaceAlias";
+ OS << " "; // "NamespaceAlias" is printed as the decl kind.
dumpBareDeclRef(NNS->getAsNamespaceAlias());
break;
case NestedNameSpecifier::TypeSpec:
diff --git a/clang/test/AST/ast-dump-decl.cpp b/clang/test/AST/ast-dump-decl.cpp
index 64e661d3383cafb..6848a2b01da2c91 100644
--- a/clang/test/AST/ast-dump-decl.cpp
+++ b/clang/test/AST/ast-dump-decl.cpp
@@ -740,7 +740,7 @@ namespace TestUsingDecl {
}
// CHECK: NamespaceDecl{{.*}} TestUsingDecl
// CHECK-NEXT: UsingDecl{{.*}} testUsingDecl::i
-// CHECK-NEXT: | `-NestedNameSpecifier NamespaceNamespace 0x{{.*}} 'testUsingDecl
+// CHECK-NEXT: | `-NestedNameSpecifier Namespace 0x{{.*}} 'testUsingDecl
// CHECK-NEXT: UsingShadowDecl{{.*}} Var{{.*}} 'i' 'int'
namespace testUnresolvedUsing {
diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp
index 4720d8fe811a722..99e02adb6b4de4b 100644
--- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp
+++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp
@@ -114,12 +114,12 @@ int main() {
// CHECK-NEXT: | | |-CallExpr [[ADDR_47:0x[a-z0-9]*]] <col:10, col:17> 'int'
// CHECK-NEXT: | | | `-ImplicitCastExpr [[ADDR_48:0x[a-z0-9]*]] <col:10, col:13> 'int (*)({{.*}})' <FunctionToPointerDecay>
// CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_49:0x[a-z0-9]*]] <col:10, col:13> 'int ({{.*}})' {{.*}}Function [[ADDR_1]] 'foo' 'int ({{.*}})'
-// CHECK-NEXT: | | | `-NestedNameSpecifier NamespaceNamespace [[ADDR_0]] 'A'
+// CHECK-NEXT: | | | `-NestedNameSpecifier Namespace [[ADDR_0]] 'A'
// CHECK-NEXT: | | `-PseudoObjectExpr [[ADDR_50:0x[a-z0-9]*]] <col:21, col:28> 'int'
// CHECK-NEXT: | | |-CallExpr [[ADDR_51:0x[a-z0-9]*]] <col:21, col:28> 'int'
// CHECK-NEXT: | | | `-ImplicitCastExpr [[ADDR_52:0x[a-z0-9]*]] <col:21, col:24> 'int (*)({{.*}})' <FunctionToPointerDecay>
// CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_53:0x[a-z0-9]*]] <col:21, col:24> 'int ({{.*}})' {{.*}}Function [[ADDR_6]] 'bar' 'int ({{.*}})'
-// CHECK-NEXT: | | | `-NestedNameSpecifier NamespaceNamespace [[ADDR_31]] 'B'
+// CHECK-NEXT: | | | `-NestedNameSpecifier Namespace [[ADDR_31]] 'B'
// CHECK-NEXT: | | `-CallExpr [[ADDR_54:0x[a-z0-9]*]] <line:34:1, line:50:28> 'int'
// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_55:0x[a-z0-9]*]] <line:34:1> 'int (*)({{.*}})' <FunctionToPointerDecay>
// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_11]] <col:1> 'int ({{.*}})' Function [[ADDR_12]] 'bar[implementation={vendor(llvm)}]' 'int ({{.*}})'
@@ -127,7 +127,7 @@ int main() {
// CHECK-NEXT: | |-CallExpr [[ADDR_57:0x[a-z0-9]*]] <col:32, col:39> 'int'
// CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_58:0x[a-z0-9]*]] <col:32, col:35> 'int (*)({{.*}})' <FunctionToPointerDecay>
// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_59:0x[a-z0-9]*]] <col:32, col:35> 'int ({{.*}})' {{.*}}Function [[ADDR_14]] 'baz' 'int ({{.*}})'
-// CHECK-NEXT: | | `-NestedNameSpecifier NamespaceNamespace [[ADDR_13]] 'C'
+// CHECK-NEXT: | | `-NestedNameSpecifier Namespace [[ADDR_13]] 'C'
// CHECK-NEXT: | `-CallExpr [[ADDR_60:0x[a-z0-9]*]] <line:42:1, line:50:39> 'int'
// CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_61:0x[a-z0-9]*]] <line:42:1> 'int (*)({{.*}})' <FunctionToPointerDecay>
// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19]] <col:1> 'int ({{.*}})' Function [[ADDR_20]] 'baz[implementation={vendor(llvm)}]' 'int ({{.*}})'
diff --git a/clang/test/AST/ast-dump-using.cpp b/clang/test/AST/ast-dump-using.cpp
index 3e3b4e5f53d8892..c007ecd8bda5839 100644
--- a/clang/test/AST/ast-dump-using.cpp
+++ b/clang/test/AST/ast-dump-using.cpp
@@ -6,7 +6,7 @@ struct S;
namespace b {
using a::S;
// CHECK: UsingDecl {{.*}} a::S
-// CHECK-NEXT: | `-NestedNameSpecifier NamespaceNamespace {{.*}} 'a'
+// CHECK-NEXT: | `-NestedNameSpecifier Namespace {{.*}} 'a'
// CHECK-NEXT: UsingShadowDecl {{.*}} implicit CXXRecord {{.*}} 'S'
// CHECK-NEXT: `-RecordType {{.*}} 'a::S'
typedef S f; // to dump the introduced type
>From 6d2e756dacfd9276775a06bdd1fea4eccace5e0f Mon Sep 17 00:00:00 2001
From: Jens Massberg <massberg at google.com>
Date: Tue, 5 Sep 2023 17:28:01 +0200
Subject: [PATCH 05/10] Initialize `ConceptReference` of new `AutoTypeLoc` with
nullptr.
Differential Revision: https://reviews.llvm.org/D159450
---
clang/lib/Sema/TreeTransform.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index cfcd19e57cf1699..7323140bc336bc2 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -6860,6 +6860,7 @@ QualType TreeTransform<Derived>::TransformAutoType(TypeLocBuilder &TLB,
AutoTypeLoc NewTL = TLB.push<AutoTypeLoc>(Result);
NewTL.setNameLoc(TL.getNameLoc());
NewTL.setRParenLoc(TL.getRParenLoc());
+ NewTL.setConceptReference(nullptr);
if (T->isConstrained()) {
DeclarationNameInfo DNI = DeclarationNameInfo(
>From 98c6c985f18edde15201676ee2640acf7dc7f55e Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq at xs4all.nl>
Date: Wed, 23 Aug 2023 21:25:13 +0200
Subject: [PATCH 06/10] [libc++][C++20 modules] Tests no wchar_t build.
Depends on D158358
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D158661
---
libcxx/cmake/caches/Generic-no-wide-characters.cmake | 1 +
libcxx/modules/std/cstdlib.inc | 2 +-
libcxx/utils/ci/buildkite-pipeline.yml | 7 +++++--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/libcxx/cmake/caches/Generic-no-wide-characters.cmake b/libcxx/cmake/caches/Generic-no-wide-characters.cmake
index 728d41086a38673..5036f6abd52e832 100644
--- a/libcxx/cmake/caches/Generic-no-wide-characters.cmake
+++ b/libcxx/cmake/caches/Generic-no-wide-characters.cmake
@@ -1 +1,2 @@
+set(LIBCXX_ENABLE_STD_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically.
set(LIBCXX_ENABLE_WIDE_CHARACTERS OFF CACHE BOOL "")
diff --git a/libcxx/modules/std/cstdlib.inc b/libcxx/modules/std/cstdlib.inc
index 11c7e8670b057c6..8840c61367c30cc 100644
--- a/libcxx/modules/std/cstdlib.inc
+++ b/libcxx/modules/std/cstdlib.inc
@@ -44,8 +44,8 @@ export namespace std {
using std::strtoull;
// [c.mb.wcs], multibyte / wide string and character conversion functions
-#ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
using std::mblen;
+#ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
using std::mbstowcs;
using std::mbtowc;
using std::wcstombs;
diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml
index 5c1010e81a9c5c9..b52074e5032f049 100644
--- a/libcxx/utils/ci/buildkite-pipeline.yml
+++ b/libcxx/utils/ci/buildkite-pipeline.yml
@@ -666,8 +666,11 @@ steps:
- "**/test-results.xml"
- "**/*.abilist"
env:
- CC: "clang-${LLVM_HEAD_VERSION}"
- CXX: "clang++-${LLVM_HEAD_VERSION}"
+ # Note: Modules require and absolute path for clang-scan-deps
+ # https://github.com/llvm/llvm-project/issues/61006
+ CC: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang"
+ CXX: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang++"
+ CMAKE: "/opt/bin/cmake"
ENABLE_CLANG_TIDY: "On"
agents:
queue: "libcxx-builders"
>From 6f8b17703da2fbabba974b82578530b152b79c26 Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq at xs4all.nl>
Date: Fri, 25 Aug 2023 19:07:59 +0200
Subject: [PATCH 07/10] [libc++][C++20 modules] Tests no except build.
Depends on D158661
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D158862
---
libcxx/cmake/caches/Generic-no-exceptions.cmake | 1 +
libcxx/docs/Modules.rst | 6 ++++++
libcxx/modules/CMakeLists.txt.in | 8 ++++----
libcxx/utils/ci/buildkite-pipeline.yml | 7 +++++--
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/libcxx/cmake/caches/Generic-no-exceptions.cmake b/libcxx/cmake/caches/Generic-no-exceptions.cmake
index f0dffef60dba082..f405f7fe9937523 100644
--- a/libcxx/cmake/caches/Generic-no-exceptions.cmake
+++ b/libcxx/cmake/caches/Generic-no-exceptions.cmake
@@ -1,2 +1,3 @@
+set(LIBCXX_ENABLE_STD_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically.
set(LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
set(LIBCXXABI_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
diff --git a/libcxx/docs/Modules.rst b/libcxx/docs/Modules.rst
index 85c42af5a62b8db..6d730cefc9fee3a 100644
--- a/libcxx/docs/Modules.rst
+++ b/libcxx/docs/Modules.rst
@@ -48,9 +48,15 @@ What works
* ``LIBCXX_ENABLE_FILESYSTEM``
* ``LIBCXX_ENABLE_RANDOM_DEVICE``
* ``LIBCXX_ENABLE_UNICODE``
+ * ``LIBCXX_ENABLE_EXCEPTIONS`` [#note-no-windows]_
* A C++20 based extension
+.. note::
+
+ .. [#note-no-windows] This configuration will probably not work on Windows
+ due to hard-coded compilation flags.
+
Some of the current limitations
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/libcxx/modules/CMakeLists.txt.in b/libcxx/modules/CMakeLists.txt.in
index 53b0d7f5f8df50c..703206e7c640579 100644
--- a/libcxx/modules/CMakeLists.txt.in
+++ b/libcxx/modules/CMakeLists.txt.in
@@ -29,10 +29,6 @@ macro(compile_define_if condition def)
endif()
endmacro()
-if(NOT @LIBCXX_ENABLE_EXCEPTIONS@ OR NOT @LIBCXXABI_ENABLE_EXCEPTIONS@)
- message(FATAL_ERROR "Modules without exception support is not yet implemented.")
-endif()
-
add_library(std)
target_sources(std
PUBLIC FILE_SET cxx_modules TYPE CXX_MODULES FILES
@@ -42,6 +38,10 @@ target_sources(std
target_compile_definitions(std PRIVATE _LIBCPP_ENABLE_EXPERIMENTAL)
target_include_directories(std SYSTEM PRIVATE @LIBCXX_CONFIGURED_INCLUDE_DIRS@)
+if (NOT @LIBCXX_ENABLE_EXCEPTIONS@)
+ target_compile_options(std PUBLIC -fno-exceptions)
+endif()
+
target_compile_options(std
PUBLIC
-nostdinc++
diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml
index b52074e5032f049..656df8434945556 100644
--- a/libcxx/utils/ci/buildkite-pipeline.yml
+++ b/libcxx/utils/ci/buildkite-pipeline.yml
@@ -705,8 +705,11 @@ steps:
- "**/test-results.xml"
- "**/*.abilist"
env:
- CC: "clang-${LLVM_HEAD_VERSION}"
- CXX: "clang++-${LLVM_HEAD_VERSION}"
+ # Note: Modules require and absolute path for clang-scan-deps
+ # https://github.com/llvm/llvm-project/issues/61006
+ CC: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang"
+ CXX: "/usr/lib/llvm-${LLVM_HEAD_VERSION}/bin/clang++"
+ CMAKE: "/opt/bin/cmake"
ENABLE_CLANG_TIDY: "On"
agents:
queue: "libcxx-builders"
>From 3065ce1ee32b779348dcfecc9fd2b280c0ca9508 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 31 Aug 2023 11:27:23 -0700
Subject: [PATCH 08/10] [RISCV][llvm-mca] Fix Fix getLMUL values
These values come from RISCVInstrInfoVPseudos.td. MF8 and MF2 were
swapped by accident.
Differential Revision: https://reviews.llvm.org/D159301
---
.../Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 4 +-
.../llvm-mca/RISCV/fractional-lmul-data.s | 55 +++++++++++++++++++
2 files changed, 57 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 70111a24c55c2d6..16f9c113e29a915 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -63,9 +63,9 @@ uint8_t RISCVLMULInstrument::getLMUL() const {
.Case("M2", 0b001)
.Case("M4", 0b010)
.Case("M8", 0b011)
- .Case("MF2", 0b101)
+ .Case("MF2", 0b111)
.Case("MF4", 0b110)
- .Case("MF8", 0b111);
+ .Case("MF8", 0b101);
}
const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW";
diff --git a/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
new file mode 100644
index 000000000000000..a72e87fab4750ef
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+
+# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
+# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
+# SPEC.
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vv v12, v12, v12
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vv v12, v12, v12
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 4
+# CHECK-NEXT: Total Cycles: 90
+# CHECK-NEXT: Total uOps: 4
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.04
+# CHECK-NEXT: IPC: 0.04
+# CHECK-NEXT: Block RThroughput: 86.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFive7FDiv
+# CHECK-NEXT: [1] - SiFive7IDiv
+# CHECK-NEXT: [2] - SiFive7PipeA
+# CHECK-NEXT: [3] - SiFive7PipeB
+# CHECK-NEXT: [4] - SiFive7PipeV
+# CHECK-NEXT: [5] - SiFive7VA
+# CHECK-NEXT: [6] - SiFive7VL
+# CHECK-NEXT: [7] - SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - 2.00 - 86.00 86.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 56.00 56.00 - - vdiv.vv v12, v12, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v12, v12, v12
>From 5b0cfa8ced90e5dab51b3cadb3e2e466c68f28c0 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 1 Sep 2023 17:19:42 -0700
Subject: [PATCH 09/10] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector
Integer Arithmetic
The intention of this test file long term is to test all valid (LMUL, SEW) pairs
for each SchedWrite class. For this reason, we do not test every single
instruction under every (LMUL, SEW) pair, since multiple instructions
may use the same SchedWrite. For example, vadd.vv and vsub.vv both use the
WriteVIALUV class.
I didn't end up getting all (LMUL, SEW) pair for each SchedWrite class though.
For example, vadd.vv and vadd.vx use WriteVIALUV and WriteVIALUX respectivley,
but I treated all Vector Single-Width Integer Add and Subtract instructions as
having the same behavior. I plan on improving the coverage as time goes on and
figured this would be a good start. If there is any class of vector integer
arithmetic instructions you'd like to see full coverage for in this patch,
please let me know.
---
.../RISCV/SiFive7/vector-integer-arithmetic.s | 2205 +++++++++++++++++
1 file changed, 2205 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
new file mode 100644
index 000000000000000..d3c1b084df35741
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
@@ -0,0 +1,2205 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+
+# The legal (SEW, LMUL) pairs on sifive-x280 are:
+# (e8, mf8) (e8, mf4) (e8, mf2) (e8, m1) (e8, m2) (e8, m4) (e8, m8)
+# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8)
+# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8)
+# (e64, m1) (e64, m2) (e64, m4) (e64, m8)
+# Widening instructions do not have e64
+# Narrowing instructions do not have e8
+
+# Vector Single-Width Integer Add and Subtract
+vsetvli zero, zero, e8, mf8, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e16, mf4, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e16, m1, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e16, m2, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e32, mf2, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e32, m1, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e32, m8, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vadd.vv v4, v8, v12
+
+# Vector Widening Integer Add/Subtract
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwaddu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwaddu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwsubu.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwsubu.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwadd.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwadd.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwsub.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwsub.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwaddu.wv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwaddu.wx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwsubu.wv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwsubu.wx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwadd.wv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwadd.wx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwsub.wv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwsub.wx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwaddu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwaddu.vx v4, v8, x10
+
+# Vector Integer Extension
+# no e8
+vsetvli zero, zero, e16, mf4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+
+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmadc.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmadc.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmadc.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsbc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vsbc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmsbc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmsbc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsbc.vv v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsbc.vx v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmadc.vvm v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmadc.vxm v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmadc.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmadc.vv v4, v8, v12
+
+# Vector Bitwise Logical Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vor.vv v4, v8, v12
+
+# Vector Single-Width Shift Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vsrl.vv v4, v8, v12
+
+# Vector Narrowing Integer Right Shift Instructions
+# no e8
+vsetvli zero, zero, e8, mf8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vnsra.wv v4, v8, v12
+
+# Vector Integer Compare Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmseq.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmseq.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmsne.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmsne.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmsne.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmsltu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmsltu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmslt.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmslt.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmsleu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmsleu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmsleu.vi v4, v8, 0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsle.vv v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsle.vx v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vmsle.vi v4, v8, 0
+vsetvli zero, zero, e32, m4, tu, mu
+vmsgtu.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmsgtu.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmsgt.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vmsgt.vi v4, v8, 0
+vsetvli zero, zero, e64, m4, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmseq.vx v4, v8, x10
+
+# Vector Integer Min/Max Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmaxu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmulhu.vx v4, v8, x10
+
+# Vector Integer Divide Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vremu.vx v4, v8, x10
+
+# Vector Widening Integer Multiply Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwmul.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmul.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwmulsu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply-Add Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vmadd.vx v4, x10, v8
+
+# Vector Widening Integer Multiply-Add Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vwmacc.vx v4, x10, v8
+
+# Vector Integer Merge Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m1, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e32, m2, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+
+# Vector Integer Move Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vmv.v.v v4, v12
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 707
+# CHECK-NEXT: Total Cycles: 15561
+# CHECK-NEXT: Total uOps: 707
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.05
+# CHECK-NEXT: IPC: 0.05
+# CHECK-NEXT: Block RThroughput: 14987.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vadd.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vadd.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vsub.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vrsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vrsub.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vadd.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwaddu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwaddu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwsubu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwsubu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwadd.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwadd.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwsub.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwsub.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwaddu.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwaddu.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwsubu.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwsubu.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwadd.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwadd.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwsub.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwsub.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwaddu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwaddu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 2.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 4.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 8.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 2.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 2.00 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 4 2.00 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 4.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 4.00 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 4 4.00 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 8.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 8.00 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 4 8.00 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 16.00 vzext.vf8 v4, v8
+# CHECK-NEXT: 1 4 16.00 vsext.vf8 v4, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmadc.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmadc.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmadc.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmsbc.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmsbc.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmadc.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vor.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vor.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vxor.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vxor.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vxor.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vor.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vor.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vxor.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vxor.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vxor.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vand.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vand.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vand.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vor.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsrl.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vsrl.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vsra.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsra.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsra.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vsrl.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsrl.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsra.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vsra.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vsra.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vsll.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vsll.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vsll.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vsrl.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 2.00 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsra.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 16.00 vnsra.wv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmseq.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmseq.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmseq.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 vmsne.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 7 4.00 vmsne.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 11 8.00 vmsne.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 19 16.00 vmsltu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmsltu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmslt.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 vmslt.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 7 4.00 vmsleu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 11 8.00 vmsleu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 19 16.00 vmsleu.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmsle.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 vmsle.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 4.00 vmsle.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 11 8.00 vmsgtu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 19 16.00 vmsgtu.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 vmsgt.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 7 4.00 vmsgt.vi v4, v8, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 11 8.00 vmseq.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 19 16.00 vmseq.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmax.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmax.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmax.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmax.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vminu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vminu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmin.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmin.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmaxu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmaxu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmulhu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmulhu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 120 120.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 60 60.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 30 30.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 240 240.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 480 480.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 960 960.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1920 1920.00 vrem.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 30 30.00 vrem.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1920 1920.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 120 120.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 240 240.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 480 480.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 960 960.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1920 1920.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 vrem.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 224 224.00 vrem.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 448 448.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 896 896.00 vdivu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 114 114.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 228 228.00 vdiv.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 456 456.00 vremu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 912 912.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmul.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmulu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmulu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vnmsub.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vnmsub.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vnmsub.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vnmsub.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vnmsac.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vnmsac.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmadd.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmadd.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 1.00 vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 2.00 vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmacc.vv v4, v12, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 vwmacc.vx v4, a0, v8
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFive7FDiv
+# CHECK-NEXT: [1] - SiFive7IDiv
+# CHECK-NEXT: [2] - SiFive7PipeA
+# CHECK-NEXT: [3] - SiFive7PipeB
+# CHECK-NEXT: [4] - SiFive7PipeV
+# CHECK-NEXT: [5] - SiFive7VA
+# CHECK-NEXT: [6] - SiFive7VL
+# CHECK-NEXT: [7] - SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - 333.00 - 14987.00 14987.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vrsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vrsub.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsub.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vrsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vrsub.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vadd.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsub.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vrsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vrsub.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwsubu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwsubu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwadd.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwadd.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwsub.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwsub.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwaddu.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwsubu.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwsubu.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwadd.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwadd.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwsub.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwsub.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwaddu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwaddu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf8 v4, v8
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf8 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf8 v4, v8
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf8 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf8 v4, v8
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf8 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf8 v4, v8
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf8 v4, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmadc.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmadc.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmadc.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmsbc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmsbc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmsbc.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmsbc.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vadc.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmadc.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmadc.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmadc.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmadc.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vor.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vor.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vor.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vxor.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vxor.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vxor.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vand.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vand.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vand.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vor.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vor.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vor.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vxor.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vxor.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vxor.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vand.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vand.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vand.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vor.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsrl.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsrl.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsrl.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsra.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsra.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsra.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsll.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsll.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsll.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsrl.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsrl.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsrl.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsra.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsra.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsra.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vsll.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vsll.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vsll.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vsrl.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnsrl.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vnsrl.wx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmsne.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmsne.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmsne.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmsltu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmsltu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmslt.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmslt.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmsleu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmsleu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmsleu.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmsle.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmsle.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmsle.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmsgtu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmsgtu.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmsgt.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmsgt.vi v4, v8, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmseq.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmseq.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmin.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmin.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmaxu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmaxu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmax.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmax.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vminu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmin.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmin.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmaxu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmaxu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmax.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmax.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vminu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vminu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmin.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmin.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmaxu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmaxu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmulh.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmulh.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmulhu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmulhu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmulh.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmulh.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmulhu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmulhsu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmulhsu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmulh.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmulh.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmulhu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 120.00 120.00 - - vdivu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 60.00 60.00 - - vdivu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 480.00 480.00 - - vremu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 960.00 960.00 - - vremu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 1920.00 1920.00 - - vrem.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 30.00 30.00 - - vrem.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1920.00 1920.00 - - vdivu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 120.00 120.00 - - vdivu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 480.00 480.00 - - vdiv.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 960.00 960.00 - - vremu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1920.00 1920.00 - - vremu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 112.00 112.00 - - vrem.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 224.00 224.00 - - vrem.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 448.00 448.00 - - vdivu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 896.00 896.00 - - vdivu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 228.00 228.00 - - vdiv.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 456.00 456.00 - - vremu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 912.00 912.00 - - vremu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmulu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmulu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmul.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vv v4, v8, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnmsac.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsac.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmadd.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmadd.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vnmsub.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnmsub.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsac.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vnmsac.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmadd.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmadd.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsub.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsub.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsac.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsac.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmadd.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmadd.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccus.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vwmaccu.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vwmaccu.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmacc.vv v4, v12, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vwmacc.vx v4, a0, v8
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12
>From 1721ea14a59af60d5caab1daa1c335f7c47b9a35 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 5 Sep 2023 09:37:08 -0700
Subject: [PATCH 10/10] fixup! [RISCV][llvm-mca] Add llvm-mca tests for SiFive7
Vector Integer Arithmetic
---
.../RISCV/SiFive7/vector-integer-arithmetic.s | 66 +++++++++----------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
index d3c1b084df35741..716f0f12f4339bb 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
@@ -755,13 +755,13 @@ vmv.v.v v4, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 707
-# CHECK-NEXT: Total Cycles: 15561
+# CHECK-NEXT: Total Cycles: 11753
# CHECK-NEXT: Total uOps: 707
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.05
-# CHECK-NEXT: IPC: 0.05
-# CHECK-NEXT: Block RThroughput: 14987.0
+# CHECK-NEXT: uOps Per Cycle: 0.06
+# CHECK-NEXT: IPC: 0.06
+# CHECK-NEXT: Block RThroughput: 11175.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -856,8 +856,8 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8
# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
-# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8
# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8
@@ -871,10 +871,10 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8
-# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8
-# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8
-# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8
+# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8
+# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8
+# CHECK-NEXT: 1 4 1.00 vzext.vf4 v4, v8
+# CHECK-NEXT: 1 4 1.00 vsext.vf4 v4, v8
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8
# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8
@@ -1056,11 +1056,11 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vsrl.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 8 2.00 vnsrl.wv v4, v8, v12
+# CHECK-NEXT: 1 8 1.00 vnsrl.wv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 8 1.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 8 2.00 vnsrl.wi v4, v8, 0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
@@ -1072,7 +1072,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 1.00 vnsrl.wi v4, v8, 0
+# CHECK-NEXT: 1 8 2.00 vnsrl.wi v4, v8, 0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
@@ -1082,7 +1082,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 8 16.00 vnsrl.wv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0
+# CHECK-NEXT: 1 8 2.00 vnsrl.wx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 8 4.00 vnsrl.wi v4, v8, 0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
@@ -1232,11 +1232,11 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vmulhu.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 120 120.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 30 30.00 vdivu.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 60 60.00 vdivu.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 30 30.00 vdiv.vv v4, v8, v12
+# CHECK-NEXT: 1 120 120.00 vdiv.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
@@ -1248,7 +1248,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 30 30.00 vrem.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1920 1920.00 vdivu.vv v4, v8, v12
+# CHECK-NEXT: 1 60 60.00 vdivu.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 120 120.00 vdivu.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
@@ -1258,7 +1258,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 960 960.00 vremu.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1920 1920.00 vremu.vx v4, v8, a0
+# CHECK-NEXT: 1 56 56.00 vremu.vx v4, v8, a0
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 112 112.00 vrem.vv v4, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
@@ -1492,7 +1492,7 @@ vmv.v.v v4, v12
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 333.00 - 14987.00 14987.00 - -
+# CHECK-NEXT: - - 333.00 - 11175.00 11175.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -1580,8 +1580,8 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8
# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
-# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8
# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8
@@ -1595,10 +1595,10 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8
-# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8
-# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8
-# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf4 v4, v8
+# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf4 v4, v8
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8
# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8
@@ -1780,11 +1780,11 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vsrl.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wi v4, v8, 0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
@@ -1796,7 +1796,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wi v4, v8, 0
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wi v4, v8, 0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
@@ -1806,7 +1806,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0
+# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: - - - - 4.00 4.00 - - vnsrl.wi v4, v8, 0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
@@ -1956,11 +1956,11 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhu.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - 120.00 120.00 - - vdivu.vv v4, v8, v12
+# CHECK-NEXT: - - - - 30.00 30.00 - - vdivu.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: - - - - 60.00 60.00 - - vdivu.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v4, v8, v12
+# CHECK-NEXT: - - - - 120.00 120.00 - - vdiv.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
@@ -1972,7 +1972,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: - - - - 30.00 30.00 - - vrem.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - 1920.00 1920.00 - - vdivu.vv v4, v8, v12
+# CHECK-NEXT: - - - - 60.00 60.00 - - vdivu.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: - - - - 120.00 120.00 - - vdivu.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
@@ -1982,7 +1982,7 @@ vmv.v.v v4, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: - - - - 960.00 960.00 - - vremu.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - 1920.00 1920.00 - - vremu.vx v4, v8, a0
+# CHECK-NEXT: - - - - 56.00 56.00 - - vremu.vx v4, v8, a0
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: - - - - 112.00 112.00 - - vrem.vv v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
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