[llvm] dd2911d - [llvm] Support assembly color highlighting for X86
Jonas Devlieghere via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 1 12:57:20 PDT 2023
Author: Jonas Devlieghere
Date: 2023-09-01T12:57:10-07:00
New Revision: dd2911d8745aacc0814b39b3382dbdb18136731e
URL: https://github.com/llvm/llvm-project/commit/dd2911d8745aacc0814b39b3382dbdb18136731e
DIFF: https://github.com/llvm/llvm-project/commit/dd2911d8745aacc0814b39b3382dbdb18136731e.diff
LOG: [llvm] Support assembly color highlighting for X86
This patch migrates the X86 backend to WithMarkup (introduced in
77d1032516e7) and adds support for color highlighting.
Differential revision: https://reviews.llvm.org/D159241
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index 4b36135da352f3..e96f9279826beb 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -36,7 +36,7 @@ using namespace llvm;
#include "X86GenAsmWriter.inc"
void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
- OS << markup("<reg:") << '%' << getRegisterName(Reg) << markup(">");
+ markup(OS, Markup::Register) << '%' << getRegisterName(Reg);
}
void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -386,7 +386,7 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
} else if (Op.isImm()) {
// Print immediates as signed values.
int64_t Imm = Op.getImm();
- O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
+ markup(O, Markup::Immediate) << '$' << formatImm(Imm);
// TODO: This should be in a helper function in the base class, so it can
// be used by other printers.
@@ -405,9 +405,9 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
- O << markup("<imm:") << '$';
+ WithMarkup M = markup(O, Markup::Immediate);
+ O << '$';
Op.getExpr()->print(O, &MAI);
- O << markup(">");
}
}
@@ -427,7 +427,7 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
- O << markup("<mem:");
+ WithMarkup M = markup(O, Markup::Memory);
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
@@ -451,19 +451,17 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
printOperand(MI, Op + X86::AddrIndexReg, O);
unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
if (ScaleVal != 1) {
- O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
- << markup(">");
+ O << ',';
+ markup(O, Markup::Immediate) << ScaleVal; // never printed in hex.
}
}
O << ')';
}
-
- O << markup(">");
}
void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
- O << markup("<mem:");
+ WithMarkup M = markup(O, Markup::Memory);
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
@@ -471,26 +469,22 @@ void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
O << "(";
printOperand(MI, Op, O);
O << ")";
-
- O << markup(">");
}
void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
- O << markup("<mem:");
+ WithMarkup M = markup(O, Markup::Memory);
O << "%es:(";
printOperand(MI, Op, O);
O << ")";
-
- O << markup(">");
}
void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &DispSpec = MI->getOperand(Op);
- O << markup("<mem:");
+ WithMarkup M = markup(O, Markup::Memory);
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
@@ -501,8 +495,6 @@ void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
assert(DispSpec.isExpr() && "non-immediate displacement?");
DispSpec.getExpr()->print(O, &MAI);
}
-
- O << markup(">");
}
void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
@@ -510,8 +502,8 @@ void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
if (MI->getOperand(Op).isExpr())
return printOperand(MI, Op, O);
- O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
- << markup(">");
+ markup(O, Markup::Immediate)
+ << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff);
}
void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
@@ -520,7 +512,7 @@ void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
unsigned Reg = Op.getReg();
// Override the default printing to print st(0) instead st.
if (Reg == X86::ST0)
- OS << markup("<reg:") << "%st(0)" << markup(">");
+ markup(OS, Markup::Register) << "%st(0)";
else
printRegName(OS, Reg);
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
index f2cb3dfc8ed028..1db55851e8f766 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -322,15 +322,13 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
- O << markup("<imm:");
if (PrintBranchImmAsAddress) {
uint64_t Target = Address + Op.getImm();
if (MAI.getCodePointerSize() == 4)
Target &= 0xffffffff;
- O << formatHex(Target);
+ markup(O, Markup::Target) << formatHex(Target);
} else
- O << formatImm(Op.getImm());
- O << markup(">");
+ markup(O, Markup::Immediate) << formatImm(Op.getImm());
} else {
assert(Op.isExpr() && "unknown pcrel immediate operand");
// If a symbolic branch target was added as a constant expression then print
@@ -338,7 +336,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
int64_t Address;
if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
- O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
+ markup(O, Markup::Immediate) << formatHex((uint64_t)Address);
} else {
// Otherwise, just print the expression.
Op.getExpr()->print(O, &MAI);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
index ecdc9090ac64d3..0705700c78173a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -34,7 +34,7 @@ using namespace llvm;
#include "X86GenAsmWriter1.inc"
void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
- OS << markup("<reg:") << getRegisterName(Reg) << markup(">");
+ markup(OS, Markup::Register) << getRegisterName(Reg);
}
void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@@ -361,7 +361,7 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Op.isReg()) {
printRegName(O, Op.getReg());
} else if (Op.isImm()) {
- O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
+ markup(O, Markup::Immediate) << formatImm((int64_t)Op.getImm());
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
O << "offset ";
@@ -388,7 +388,8 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
- O << markup("<mem:") << '[';
+ WithMarkup M = markup(O, Markup::Memory);
+ O << '[';
bool NeedPlus = false;
if (BaseReg.getReg()) {
@@ -419,28 +420,33 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
DispVal = -DispVal;
}
}
- O << markup("<imm:") << formatImm(DispVal) << markup(">");
+ markup(O, Markup::Immediate) << formatImm(DispVal);
}
}
- O << ']' << markup(">");
+ O << ']';
}
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
- O << markup("<mem:") << '[';
+
+ WithMarkup M = markup(O, Markup::Memory);
+ O << '[';
printOperand(MI, Op, O);
- O << ']' << markup(">");
+ O << ']';
}
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// DI accesses are always ES-based.
- O << "es:" << markup("<mem:") << '[';
+ O << "es:";
+
+ WithMarkup M = markup(O, Markup::Memory);
+ O << '[';
printOperand(MI, Op, O);
- O << ']' << markup(">");
+ O << ']';
}
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
@@ -450,16 +456,17 @@ void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
- O << markup("<mem:") << '[';
+ WithMarkup M = markup(O, Markup::Memory);
+ O << '[';
if (DispSpec.isImm()) {
- O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
+ markup(O, Markup::Immediate) << formatImm(DispSpec.getImm());
} else {
assert(DispSpec.isExpr() && "non-immediate displacement?");
DispSpec.getExpr()->print(O, &MAI);
}
- O << ']' << markup(">");
+ O << ']';
}
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
@@ -467,8 +474,7 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
if (MI->getOperand(Op).isExpr())
return MI->getOperand(Op).getExpr()->print(O, &MAI);
- O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
- << markup(">");
+ markup(O, Markup::Immediate) << formatImm(MI->getOperand(Op).getImm() & 0xff);
}
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
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