[PATCH] D159190: [RISCV]Combine to make the fixed vector vadd of splats are scalarized

[Luke Lau via Phabricator via llvm-commits]

luke added a comment.

In D159190#4634146 <https://reviews.llvm.org/D159190#4634146>, @liaolucy wrote:

> Another solution, enabling the isExtractVecEltCheap when XlenVT == vector_element_type, It's working for pr65068.ll.

It looks like isExtractVecEltCheap might be meant for "free" extracts:

> For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.

But on RISC-V we'll need a vmv.x.s, so I don't think that qualifies as "free". But this is only if it's coming from a vector_shuffle if I understand correctly: build_vector splats and splat_vector splats should indeed be free because the extract_vector_elt will be combined away.

> But I'm worried about the side effects of this approach. How to test fixed length vectors? Any suggestions?
>
> Try to use the command: -march=rv64gcv -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 , but the llvm ir scalable(not fixed length vectors.)

Is pr65068.ll not already testing this on fixed length vectors?


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