[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX node can be simplified to a OR or AND node

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2161
+    case ISD::SMAX:
+      // TODO: Add KnownBits::sge/sgt handling.
+      break;
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goldstein.w.n wrote:
> Should compute Known for `smin`/`smax`? Imo also just fill in the TODO. Its not much code required.
Adding smin/smax knownbits handling adds a couple of unrelated changes - I'd prefer to handle that separately. If you prefer, I can refactor the existing min/max cases into this new layout first (with existing functionality) and then fix the missing knownbits handling first?


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  https://reviews.llvm.org/D158364/new/

https://reviews.llvm.org/D158364