[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll:860
 }
+
+define <vscale x 16 x i1> @ctpop_nxv16i32_ult_two(<vscale x 16 x i32> %va) {
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craig.topper wrote:
> These tests already pass.
> The vector part of this isn't tested.

Should I remove these useless tests? We always emit `vcpop` for the vector part.



Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390