[PATCH] D158568: [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland updated this revision to Diff 553284.
michaelmaitland added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158568/new/

https://reviews.llvm.org/D158568

Files:
  llvm/include/llvm/CodeGen/MachineScheduler.h
  llvm/include/llvm/CodeGen/MachineTraceMetrics.h
  llvm/include/llvm/MC/MCSchedule.h
  llvm/include/llvm/MCA/HWEventListener.h
  llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
  llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
  llvm/include/llvm/MCA/Support.h
  llvm/include/llvm/Target/TargetSchedule.td
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/CodeGen/MachineTraceMetrics.cpp
  llvm/lib/MC/MCSchedule.cpp
  llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
  llvm/lib/MCA/HardwareUnits/Scheduler.cpp
  llvm/lib/MCA/InstrBuilder.cpp
  llvm/lib/MCA/Stages/ExecuteStage.cpp
  llvm/lib/MCA/Stages/InstructionTables.cpp
  llvm/lib/MCA/Support.cpp
  llvm/lib/Target/AArch64/AArch64SchedA510.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/lib/Target/ARM/ARMSchedule.td
  llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
  llvm/lib/Target/ARM/ARMScheduleA9.td
  llvm/lib/Target/ARM/ARMScheduleM55.td
  llvm/lib/Target/ARM/ARMScheduleM85.td
  llvm/lib/Target/ARM/ARMScheduleR52.td
  llvm/lib/Target/ARM/ARMScheduleSwift.td
  llvm/lib/Target/Mips/MipsScheduleGeneric.td
  llvm/lib/Target/Mips/MipsScheduleP5600.td
  llvm/lib/Target/PowerPC/PPCScheduleP10.td
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
  llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
  llvm/lib/Target/X86/X86SchedAlderlakeP.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedIceLake.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSapphireRapids.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86Schedule.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td
  llvm/lib/Target/X86/X86ScheduleZnver3.td
  llvm/lib/Target/X86/X86ScheduleZnver4.td
  llvm/test/TableGen/AcquireAtCycle.td
  llvm/test/TableGen/StartAtCycle.td
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
  llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
  llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
  llvm/tools/llvm-mca/Views/ResourcePressureView.h
  llvm/utils/TableGen/SubtargetEmitter.cpp