[llvm] 71bfec7 - Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 15:38:27 PDT 2023
Author: Michael Maitland
Date: 2023-08-24T15:37:27-07:00
New Revision: 71bfec762bd970e7834f58c158ddc15f93402d7a
URL: https://github.com/llvm/llvm-project/commit/71bfec762bd970e7834f58c158ddc15f93402d7a
DIFF: https://github.com/llvm/llvm-project/commit/71bfec762bd970e7834f58c158ddc15f93402d7a.diff
LOG: Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 5b854f2c23ea1b000cb4cac4c0fea77326c03d43.
Build still failing.
Added:
llvm/test/TableGen/StartAtCycle.td
Modified:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/include/llvm/CodeGen/MachineTraceMetrics.h
llvm/include/llvm/MC/MCSchedule.h
llvm/include/llvm/MCA/HWEventListener.h
llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
llvm/include/llvm/MCA/Support.h
llvm/include/llvm/Target/TargetSchedule.td
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/MC/MCSchedule.cpp
llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
llvm/lib/MCA/HardwareUnits/Scheduler.cpp
llvm/lib/MCA/InstrBuilder.cpp
llvm/lib/MCA/Stages/ExecuteStage.cpp
llvm/lib/MCA/Stages/InstructionTables.cpp
llvm/lib/MCA/Support.cpp
llvm/lib/Target/AArch64/AArch64SchedA510.td
llvm/lib/Target/AArch64/AArch64SchedA53.td
llvm/lib/Target/AArch64/AArch64SchedA55.td
llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
llvm/lib/Target/AArch64/AArch64SchedA64FX.td
llvm/lib/Target/AArch64/AArch64SchedCyclone.td
llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
llvm/lib/Target/AArch64/AArch64SchedThunderX.td
llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/SISchedule.td
llvm/lib/Target/ARM/ARMSchedule.td
llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
llvm/lib/Target/ARM/ARMScheduleA9.td
llvm/lib/Target/ARM/ARMScheduleM55.td
llvm/lib/Target/ARM/ARMScheduleM85.td
llvm/lib/Target/ARM/ARMScheduleR52.td
llvm/lib/Target/ARM/ARMScheduleSwift.td
llvm/lib/Target/Mips/MipsScheduleGeneric.td
llvm/lib/Target/Mips/MipsScheduleP5600.td
llvm/lib/Target/PowerPC/PPCScheduleP10.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/lib/Target/X86/X86SchedAlderlakeP.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedIceLake.td
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/lib/Target/X86/X86SchedSapphireRapids.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86Schedule.td
llvm/lib/Target/X86/X86ScheduleAtom.td
llvm/lib/Target/X86/X86ScheduleBdVer2.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/lib/Target/X86/X86ScheduleZnver2.td
llvm/lib/Target/X86/X86ScheduleZnver3.td
llvm/lib/Target/X86/X86ScheduleZnver4.td
llvm/tools/llvm-exegesis/lib/Analysis.cpp
llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
llvm/tools/llvm-mca/Views/ResourcePressureView.h
llvm/utils/TableGen/SubtargetEmitter.cpp
Removed:
llvm/test/TableGen/AcquireAtCycle.td
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 9f16cf5d5bc387..c950a9ac5c3879 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -656,15 +656,15 @@ class ResourceSegments {
///
/// Consider an instruction that uses resources X0, X1 and X2 as follows:
///
- /// X0 X1 X1 X2 +--------+-------------+--------------+
- /// |Resource|AcquireAtCycle|ReleaseAtCycle|
- /// +--------+-------------+--------------+
- /// | X0 | 0 | 1 |
- /// +--------+-------------+--------------+
- /// | X1 | 1 | 3 |
- /// +--------+-------------+--------------+
- /// | X2 | 3 | 4 |
- /// +--------+-------------+--------------+
+ /// X0 X1 X1 X2 +--------+------------+------+
+ /// |Resource|StartAtCycle|Cycles|
+ /// +--------+------------+------+
+ /// | X0 | 0 | 1 |
+ /// +--------+------------+------+
+ /// | X1 | 1 | 3 |
+ /// +--------+------------+------+
+ /// | X2 | 3 | 4 |
+ /// +--------+------------+------+
///
/// If we can schedule the instruction at cycle C, we need to
/// compute the interval of the resource as follows:
@@ -685,7 +685,7 @@ class ResourceSegments {
/// of an instruction that can be scheduled at cycle C in top-down
/// scheduling is:
///
- /// [C+AcquireAtCycle, C+ReleaseAtCycle)
+ /// [C+StartAtCycle, C+Cycles)
///
///
/// # BOTTOM UP SCHEDULING
@@ -709,20 +709,20 @@ class ResourceSegments {
/// of an instruction that can be scheduled at cycle C in bottom-up
/// scheduling is:
///
- /// [C-ReleaseAtCycle+1, C-AcquireAtCycle+1)
+ /// [C-Cycle+1, C-StartAtCycle+1)
///
///
/// NOTE: In both cases, the number of cycles booked by a
- /// resources is the value (ReleaseAtCycle - AcquireAtCycle).
- static IntervalTy getResourceIntervalBottom(unsigned C, unsigned AcquireAtCycle,
- unsigned ReleaseAtCycle) {
- return std::make_pair<long, long>((long)C - (long)ReleaseAtCycle + 1L,
- (long)C - (long)AcquireAtCycle + 1L);
+ /// resources is the value (Cycle - StartAtCycles).
+ static IntervalTy getResourceIntervalBottom(unsigned C, unsigned StartAtCycle,
+ unsigned Cycle) {
+ return std::make_pair<long, long>((long)C - (long)Cycle + 1L,
+ (long)C - (long)StartAtCycle + 1L);
}
- static IntervalTy getResourceIntervalTop(unsigned C, unsigned AcquireAtCycle,
- unsigned ReleaseAtCycle) {
- return std::make_pair<long, long>((long)C + (long)AcquireAtCycle,
- (long)C + (long)ReleaseAtCycle);
+ static IntervalTy getResourceIntervalTop(unsigned C, unsigned StartAtCycle,
+ unsigned Cycle) {
+ return std::make_pair<long, long>((long)C + (long)StartAtCycle,
+ (long)C + (long)Cycle);
}
private:
@@ -730,7 +730,7 @@ class ResourceSegments {
///
/// The function uses the \param IntervalBuider [*] to build a
/// resource interval [a, b[ out of the input parameters \param
- /// CurrCycle, \param AcquireAtCycle and \param ReleaseAtCycle.
+ /// CurrCycle, \param StartAtCycle and \param Cycle.
///
/// The function then loops through the intervals in the ResourceSegments
/// and shifts the interval [a, b[ and the ReturnCycle to the
@@ -744,7 +744,7 @@ class ResourceSegments {
/// c 1 2 3 4 5 6 7 8 9 10 ... ---> (time
/// flow)
/// ResourceSegments... [---) [-------) [-----------)
- /// c [1 3[ -> AcquireAtCycle=1, ReleaseAtCycle=3
+ /// c [1 3[ -> StartAtCycle=1, Cycles=3
/// ++c [1 3)
/// ++c [1 3)
/// ++c [1 3)
@@ -772,25 +772,24 @@ class ResourceSegments {
/// [*] See \ref `getResourceIntervalTop` and
/// \ref `getResourceIntervalBottom` to see how such resource intervals
/// are built.
- unsigned getFirstAvailableAt(
- unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle,
- std::function<IntervalTy(unsigned, unsigned, unsigned)> IntervalBuilder)
- const;
+ unsigned
+ getFirstAvailableAt(unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
+ std::function<IntervalTy(unsigned, unsigned, unsigned)>
+ IntervalBuilder) const;
public:
/// getFirstAvailableAtFromBottom and getFirstAvailableAtFromTop
/// should be merged in a single function in which a function that
/// creates the `NewInterval` is passed as a parameter.
unsigned getFirstAvailableAtFromBottom(unsigned CurrCycle,
- unsigned AcquireAtCycle,
- unsigned ReleaseAtCycle) const {
- return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
+ unsigned StartAtCycle,
+ unsigned Cycle) const {
+ return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
getResourceIntervalBottom);
}
- unsigned getFirstAvailableAtFromTop(unsigned CurrCycle,
- unsigned AcquireAtCycle,
- unsigned ReleaseAtCycle) const {
- return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
+ unsigned getFirstAvailableAtFromTop(unsigned CurrCycle, unsigned StartAtCycle,
+ unsigned Cycle) const {
+ return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
getResourceIntervalTop);
}
@@ -1007,13 +1006,13 @@ class SchedBoundary {
unsigned getLatencyStallCycles(SUnit *SU);
unsigned getNextResourceCycleByInstance(unsigned InstanceIndex,
- unsigned ReleaseAtCycle,
- unsigned AcquireAtCycle);
+ unsigned Cycles,
+ unsigned StartAtCycle);
std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
unsigned PIdx,
- unsigned ReleaseAtCycle,
- unsigned AcquireAtCycle);
+ unsigned Cycles,
+ unsigned StartAtCycle);
bool isUnbufferedGroup(unsigned PIdx) const {
return SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin &&
diff --git a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
index fce78581a48c4c..63e4210b2a860e 100644
--- a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
+++ b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
@@ -143,7 +143,7 @@ class MachineTraceMetrics : public MachineFunctionPass {
/// The getResources() function above must have been called first.
///
/// These numbers have already been scaled by SchedModel.getResourceFactor().
- ArrayRef<unsigned> getProcReleaseAtCycles(unsigned MBBNum) const;
+ ArrayRef<unsigned> getProcResourceCycles(unsigned MBBNum) const;
/// A virtual register or regunit required by a basic block or its trace
/// successors.
@@ -404,9 +404,9 @@ class MachineTraceMetrics : public MachineFunctionPass {
// Cycles consumed on each processor resource per block.
// The number of processor resource kinds is constant for a given subtarget,
// but it is not known at compile time. The number of cycles consumed by
- // block B on processor resource R is at ProcReleaseAtCycles[B*Kinds + R]
+ // block B on processor resource R is at ProcResourceCycles[B*Kinds + R]
// where Kinds = SchedModel.getNumProcResourceKinds().
- SmallVector<unsigned, 0> ProcReleaseAtCycles;
+ SmallVector<unsigned, 0> ProcResourceCycles;
// One ensemble per strategy.
Ensemble
diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h
index 98ebe42cfd133b..e6cf27ce2d6513 100644
--- a/llvm/include/llvm/MC/MCSchedule.h
+++ b/llvm/include/llvm/MC/MCSchedule.h
@@ -60,21 +60,24 @@ struct MCProcResourceDesc {
/// Identify one of the processor resource kinds consumed by a
/// particular scheduling class for the specified number of cycles.
+/// TODO: consider renaming the field `StartAtCycle` and `Cycles` to
+/// `AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
+/// fact that resource allocation is now represented as an interval,
+/// relatively to the issue cycle of the instruction.
struct MCWriteProcResEntry {
uint16_t ProcResourceIdx;
/// Cycle at which the resource will be released by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
- uint16_t ReleaseAtCycle;
- /// Cycle at which the resource will be aquired by an instruction,
+ uint16_t Cycles;
+ /// Cycle at which the resource will be grabbed by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
- uint16_t AcquireAtCycle;
+ uint16_t StartAtCycle;
bool operator==(const MCWriteProcResEntry &Other) const {
- return ProcResourceIdx == Other.ProcResourceIdx &&
- ReleaseAtCycle == Other.ReleaseAtCycle &&
- AcquireAtCycle == Other.AcquireAtCycle;
+ return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles &&
+ StartAtCycle == Other.StartAtCycle;
}
};
@@ -223,12 +226,12 @@ struct MCExtraProcessorInfo {
/// consistent. Inaccuracies arise when instructions have
diff erent execution
/// delays relative to each other, in addition to their intrinsic latency. Those
/// special cases can be handled by TableGen constructs such as, ReadAdvance,
-/// which reduces latency when reading data, and ReleaseAtCycles, which consumes
+/// which reduces latency when reading data, and ResourceCycles, which consumes
/// a processor resource when writing data for a number of abstract
/// cycles.
///
/// TODO: One tool currently missing is the ability to add a delay to
-/// ReleaseAtCycles. That would be easy to add and would likely cover all cases
+/// ResourceCycles. That would be easy to add and would likely cover all cases
/// currently handled by the legacy itinerary tables.
///
/// A note on out-of-order execution and, more generally, instruction
diff --git a/llvm/include/llvm/MCA/HWEventListener.h b/llvm/include/llvm/MCA/HWEventListener.h
index a27b1f12e6a6ee..a24b90654e2f19 100644
--- a/llvm/include/llvm/MCA/HWEventListener.h
+++ b/llvm/include/llvm/MCA/HWEventListener.h
@@ -63,7 +63,7 @@ class HWInstructionEvent {
// ResourceRef::second is a bitmask of the referenced sub-unit of the resource.
using ResourceRef = std::pair<uint64_t, uint64_t>;
-using ResourceUse = std::pair<ResourceRef, ReleaseAtCycles>;
+using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
class HWInstructionIssuedEvent : public HWInstructionEvent {
public:
diff --git a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
index 0e3f16d2a490b5..88085d0bc453b8 100644
--- a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
+++ b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
@@ -430,7 +430,7 @@ class ResourceManager {
void issueInstruction(
const InstrDesc &Desc,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);
diff --git a/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h b/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
index 272f6b197868b9..8c0ad2699b8db8 100644
--- a/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
+++ b/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
@@ -136,7 +136,7 @@ class Scheduler : public HardwareUnit {
/// Issue an instruction without updating the ready queue.
void issueInstructionImpl(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
// Identify instructions that have finished executing, and remove them from
// the IssuedSet. References to executed instructions are added to input
@@ -202,7 +202,7 @@ class Scheduler : public HardwareUnit {
/// result of this event.
void issueInstruction(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
SmallVectorImpl<InstRef> &Pending,
SmallVectorImpl<InstRef> &Ready);
diff --git a/llvm/include/llvm/MCA/Support.h b/llvm/include/llvm/MCA/Support.h
index e3c155435e2347..e5e6278171051f 100644
--- a/llvm/include/llvm/MCA/Support.h
+++ b/llvm/include/llvm/MCA/Support.h
@@ -48,12 +48,12 @@ template <typename T> char InstructionError<T>::ID;
/// number of resources, are kept separate. This is used by the
/// ResourcePressureView to calculate the average resource cycles
/// per instruction/iteration.
-class ReleaseAtCycles {
+class ResourceCycles {
unsigned Numerator, Denominator;
public:
- ReleaseAtCycles() : Numerator(0), Denominator(1) {}
- ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
+ ResourceCycles() : Numerator(0), Denominator(1) {}
+ ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
: Numerator(Cycles), Denominator(ResourceUnits) {}
operator double() const {
@@ -67,7 +67,7 @@ class ReleaseAtCycles {
// Add the components of RHS to this instance. Instead of calculating
// the final value here, we keep track of the numerator and denominator
// separately, to reduce floating point error.
- ReleaseAtCycles &operator+=(const ReleaseAtCycles &RHS);
+ ResourceCycles &operator+=(const ResourceCycles &RHS);
};
/// Populates vector Masks with processor resource masks.
@@ -105,7 +105,7 @@ inline unsigned getResourceStateIndex(uint64_t Mask) {
/// Compute the reciprocal block throughput from a set of processor resource
/// cycles. The reciprocal block throughput is computed as the MAX between:
/// - NumMicroOps / DispatchWidth
-/// - ProcReleaseAtCycles / #ProcResourceUnits (for every consumed resource).
+/// - ProcResourceCycles / #ProcResourceUnits (for every consumed resource).
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
unsigned NumMicroOps,
ArrayRef<unsigned> ProcResourceUsage);
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 949baa5d2105c4..f5aa105ec0cbbf 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -147,7 +147,7 @@ class ProcResourceKind;
// changes this to an in-order issue/dispatch resource. In this case,
// the scheduler counts down from the cycle that the instruction
// issues in-order, forcing a stall whenever a subsequent instruction
-// requires the same resource until the number of ReleaseAtCycles
+// requires the same resource until the number of ResourceCycles
// specified in WriteRes expire. Setting BufferSize=1 changes this to
// an in-order latency resource. In this case, the scheduler models
// producer/consumer stalls between instructions that use the
@@ -254,14 +254,8 @@ class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
// SchedModel ties these resources to a processor.
class ProcWriteResources<list<ProcResourceKind> resources> {
list<ProcResourceKind> ProcResources = resources;
- /// Cycle at which the resource will be released by an instruction,
- /// relatively to the cycle in which the instruction is issued
- /// (assuming no stalls inbetween).
- list<int> ReleaseAtCycles = [];
- /// Cycle at which the resource will be aquired by an instruction,
- /// relatively to the cycle in which the instruction is issued
- /// (assuming no stalls inbetween).
- list<int> AcquireAtCycles = [];
+ list<int> ResourceCycles = [];
+ list<int> StartAtCycles = [];
int Latency = 1;
int NumMicroOps = 1;
bit BeginGroup = false;
@@ -291,12 +285,12 @@ class ProcWriteResources<list<ProcResourceKind> resources> {
// itinerary classes to the subtarget's SchedWrites.
//
// ProcResources indicates the set of resources consumed by the write.
-// Optionally, ReleaseAtCycles indicates the number of cycles the
-// resource is consumed. Each ReleaseAtCycles item is paired with the
-// ProcResource item at the same position in its list. ReleaseAtCycles
+// Optionally, ResourceCycles indicates the number of cycles the
+// resource is consumed. Each ResourceCycles item is paired with the
+// ProcResource item at the same position in its list. ResourceCycles
// can be `[]`: in that case, all resources are consumed for a single
// cycle, regardless of latency, which models a fully pipelined processing
-// unit. A value of 0 for ReleaseAtCycles means that the resource must
+// unit. A value of 0 for ResourceCycles means that the resource must
// be available but is not consumed, which is only relevant for
// unbuffered resources.
//
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index adcbf65259cdda..c7e7497dab368a 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1039,7 +1039,7 @@ struct FuncUnitSorter {
for (const MCWriteProcResEntry &PRE :
make_range(STI->getWriteProcResBegin(SCDesc),
STI->getWriteProcResEnd(SCDesc))) {
- if (!PRE.ReleaseAtCycle)
+ if (!PRE.Cycles)
continue;
const MCProcResourceDesc *ProcResource =
STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
@@ -1082,7 +1082,7 @@ struct FuncUnitSorter {
for (const MCWriteProcResEntry &PRE :
make_range(STI->getWriteProcResBegin(SCDesc),
STI->getWriteProcResEnd(SCDesc))) {
- if (!PRE.ReleaseAtCycle)
+ if (!PRE.Cycles)
continue;
Resources[PRE.ProcResourceIdx]++;
}
@@ -3092,7 +3092,7 @@ void ResourceManager::reserveResources(const MCSchedClassDesc *SCDesc,
assert(!UseDFA);
for (const MCWriteProcResEntry &PRE : make_range(
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
- for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
+ for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
++MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@@ -3104,7 +3104,7 @@ void ResourceManager::unreserveResources(const MCSchedClassDesc *SCDesc,
assert(!UseDFA);
for (const MCWriteProcResEntry &PRE : make_range(
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
- for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
+ for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
--MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@@ -3220,10 +3220,10 @@ int ResourceManager::calculateResMII() const {
if (SwpDebugResource) {
const MCProcResourceDesc *Desc =
SM.getProcResource(PRE.ProcResourceIdx);
- dbgs() << Desc->Name << ": " << PRE.ReleaseAtCycle << ", ";
+ dbgs() << Desc->Name << ": " << PRE.Cycles << ", ";
}
});
- ResourceCount[PRE.ProcResourceIdx] += PRE.ReleaseAtCycle;
+ ResourceCount[PRE.ProcResourceIdx] += PRE.Cycles;
}
LLVM_DEBUG(if (SwpDebugResource) dbgs() << "\n");
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index da3e4bcbe267d3..556f0036bed3ec 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -980,8 +980,8 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const {
for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC);
PI != PE; ++PI) {
- if (SU->TopReadyCycle + PI->ReleaseAtCycle - 1 > LastCycle)
- LastCycle = SU->TopReadyCycle + PI->ReleaseAtCycle - 1;
+ if (SU->TopReadyCycle + PI->Cycles - 1 > LastCycle)
+ LastCycle = SU->TopReadyCycle + PI->Cycles - 1;
}
}
// Print the header with the cycles
@@ -1017,20 +1017,19 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const {
llvm::stable_sort(ResourcesIt,
[](const MCWriteProcResEntry &LHS,
const MCWriteProcResEntry &RHS) -> bool {
- return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
- (LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
- LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
+ return LHS.StartAtCycle < RHS.StartAtCycle ||
+ (LHS.StartAtCycle == RHS.StartAtCycle &&
+ LHS.Cycles < RHS.Cycles);
});
for (const MCWriteProcResEntry &PI : ResourcesIt) {
C = FirstCycle;
const std::string ResName =
SchedModel.getResourceName(PI.ProcResourceIdx);
dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
- for (; C < SU->TopReadyCycle + PI.AcquireAtCycle; ++C) {
+ for (; C < SU->TopReadyCycle + PI.StartAtCycle; ++C) {
dbgs() << llvm::left_justify("|", ColWidth);
}
- for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
- ++I, ++C)
+ for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, ++C)
dbgs() << llvm::left_justify("| x", ColWidth);
while (C++ <= LastCycle)
dbgs() << llvm::left_justify("|", ColWidth);
@@ -1062,8 +1061,8 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const {
for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC);
PI != PE; ++PI) {
- if ((int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1 < LastCycle)
- LastCycle = (int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1;
+ if ((int)SU->BotReadyCycle - PI->Cycles + 1 < LastCycle)
+ LastCycle = (int)SU->BotReadyCycle - PI->Cycles + 1;
}
}
// Print the header with the cycles
@@ -1098,20 +1097,19 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const {
llvm::stable_sort(ResourcesIt,
[](const MCWriteProcResEntry &LHS,
const MCWriteProcResEntry &RHS) -> bool {
- return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
- (LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
- LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
+ return LHS.StartAtCycle < RHS.StartAtCycle ||
+ (LHS.StartAtCycle == RHS.StartAtCycle &&
+ LHS.Cycles < RHS.Cycles);
});
for (const MCWriteProcResEntry &PI : ResourcesIt) {
C = FirstCycle;
const std::string ResName =
SchedModel.getResourceName(PI.ProcResourceIdx);
dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
- for (; C > ((int)SU->BotReadyCycle - (int)PI.AcquireAtCycle); --C) {
+ for (; C > ((int)SU->BotReadyCycle - (int)PI.StartAtCycle); --C) {
dbgs() << llvm::left_justify("|", ColWidth);
}
- for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
- ++I, --C)
+ for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, --C)
dbgs() << llvm::left_justify("| x", ColWidth);
while (C-- >= LastCycle)
dbgs() << llvm::left_justify("|", ColWidth);
@@ -2239,9 +2237,8 @@ init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
unsigned PIdx = PI->ProcResourceIdx;
unsigned Factor = SchedModel->getResourceFactor(PIdx);
- assert(PI->ReleaseAtCycle >= PI->AcquireAtCycle);
- RemainingCounts[PIdx] +=
- (Factor * (PI->ReleaseAtCycle - PI->AcquireAtCycle));
+ assert(PI->Cycles >= PI->StartAtCycle);
+ RemainingCounts[PIdx] += (Factor * (PI->Cycles - PI->StartAtCycle));
}
}
}
@@ -2294,15 +2291,15 @@ unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
/// Compute the next cycle at which the given processor resource unit
/// can be scheduled.
unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
- unsigned ReleaseAtCycle,
- unsigned AcquireAtCycle) {
+ unsigned Cycles,
+ unsigned StartAtCycle) {
if (SchedModel && SchedModel->enableIntervals()) {
if (isTop())
return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromTop(
- CurrCycle, AcquireAtCycle, ReleaseAtCycle);
+ CurrCycle, StartAtCycle, Cycles);
return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromBottom(
- CurrCycle, AcquireAtCycle, ReleaseAtCycle);
+ CurrCycle, StartAtCycle, Cycles);
}
unsigned NextUnreserved = ReservedCycles[InstanceIdx];
@@ -2311,7 +2308,7 @@ unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
return CurrCycle;
// For bottom-up scheduling add the cycles needed for the current operation.
if (!isTop())
- NextUnreserved = std::max(CurrCycle, NextUnreserved + ReleaseAtCycle);
+ NextUnreserved = std::max(CurrCycle, NextUnreserved + Cycles);
return NextUnreserved;
}
@@ -2320,8 +2317,7 @@ unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
/// instance in the reserved cycles vector.
std::pair<unsigned, unsigned>
SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
- unsigned ReleaseAtCycle,
- unsigned AcquireAtCycle) {
+ unsigned Cycles, unsigned StartAtCycle) {
if (MischedDetailResourceBooking) {
LLVM_DEBUG(dbgs() << " Resource booking (@" << CurrCycle << "c): \n");
LLVM_DEBUG(dumpReservedCycles());
@@ -2350,15 +2346,15 @@ SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
make_range(SchedModel->getWriteProcResBegin(SC),
SchedModel->getWriteProcResEnd(SC)))
if (ResourceGroupSubUnitMasks[PIdx][PE.ProcResourceIdx])
- return std::make_pair(getNextResourceCycleByInstance(
- StartIndex, ReleaseAtCycle, AcquireAtCycle),
- StartIndex);
+ return std::make_pair(
+ getNextResourceCycleByInstance(StartIndex, Cycles, StartAtCycle),
+ StartIndex);
auto SubUnits = SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin;
for (unsigned I = 0, End = NumberOfInstances; I < End; ++I) {
unsigned NextUnreserved, NextInstanceIdx;
std::tie(NextUnreserved, NextInstanceIdx) =
- getNextResourceCycle(SC, SubUnits[I], ReleaseAtCycle, AcquireAtCycle);
+ getNextResourceCycle(SC, SubUnits[I], Cycles, StartAtCycle);
if (MinNextUnreserved > NextUnreserved) {
InstanceIdx = NextInstanceIdx;
MinNextUnreserved = NextUnreserved;
@@ -2370,7 +2366,7 @@ SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
for (unsigned I = StartIndex, End = StartIndex + NumberOfInstances; I < End;
++I) {
unsigned NextUnreserved =
- getNextResourceCycleByInstance(I, ReleaseAtCycle, AcquireAtCycle);
+ getNextResourceCycleByInstance(I, Cycles, StartAtCycle);
if (MischedDetailResourceBooking)
LLVM_DEBUG(dbgs() << " Instance " << I - StartIndex << " available @"
<< NextUnreserved << "c\n");
@@ -2427,14 +2423,14 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
make_range(SchedModel->getWriteProcResBegin(SC),
SchedModel->getWriteProcResEnd(SC))) {
unsigned ResIdx = PE.ProcResourceIdx;
- unsigned ReleaseAtCycle = PE.ReleaseAtCycle;
- unsigned AcquireAtCycle = PE.AcquireAtCycle;
+ unsigned Cycles = PE.Cycles;
+ unsigned StartAtCycle = PE.StartAtCycle;
unsigned NRCycle, InstanceIdx;
std::tie(NRCycle, InstanceIdx) =
- getNextResourceCycle(SC, ResIdx, ReleaseAtCycle, AcquireAtCycle);
+ getNextResourceCycle(SC, ResIdx, Cycles, StartAtCycle);
if (NRCycle > CurrCycle) {
#if LLVM_ENABLE_ABI_BREAKING_CHECKS
- MaxObservedStall = std::max(ReleaseAtCycle, MaxObservedStall);
+ MaxObservedStall = std::max(Cycles, MaxObservedStall);
#endif
LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(ResIdx)
@@ -2576,22 +2572,18 @@ void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
/// Add the given processor resource to this scheduled zone.
///
-/// \param ReleaseAtCycle indicates the number of consecutive (non-pipelined)
-/// cycles during which this resource is released.
-///
-/// \param AcquireAtCycle indicates the number of consecutive (non-pipelined)
-/// cycles at which the resource is aquired after issue (assuming no stalls).
+/// \param Cycles indicates the number of consecutive (non-pipelined) cycles
+/// during which this resource is consumed.
///
/// \return the next cycle at which the instruction may execute without
/// oversubscribing resources.
unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx,
- unsigned ReleaseAtCycle,
- unsigned NextCycle,
- unsigned AcquireAtCycle) {
+ unsigned Cycles, unsigned NextCycle,
+ unsigned StartAtCycle) {
unsigned Factor = SchedModel->getResourceFactor(PIdx);
- unsigned Count = Factor * (ReleaseAtCycle- AcquireAtCycle);
+ unsigned Count = Factor * (Cycles - StartAtCycle);
LLVM_DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) << " +"
- << ReleaseAtCycle << "x" << Factor << "u\n");
+ << Cycles << "x" << Factor << "u\n");
// Update Executed resources counts.
incExecutedResources(PIdx, Count);
@@ -2610,7 +2602,7 @@ unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx,
// For reserved resources, record the highest cycle using the resource.
unsigned NextAvailable, InstanceIdx;
std::tie(NextAvailable, InstanceIdx) =
- getNextResourceCycle(SC, PIdx, ReleaseAtCycle, AcquireAtCycle);
+ getNextResourceCycle(SC, PIdx, Cycles, StartAtCycle);
if (NextAvailable > CurrCycle) {
LLVM_DEBUG(dbgs() << " Resource conflict: "
<< SchedModel->getResourceName(PIdx)
@@ -2689,9 +2681,8 @@ void SchedBoundary::bumpNode(SUnit *SU) {
for (TargetSchedModel::ProcResIter
PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
- unsigned RCycle =
- countResource(SC, PI->ProcResourceIdx, PI->ReleaseAtCycle, NextCycle,
- PI->AcquireAtCycle);
+ unsigned RCycle = countResource(SC, PI->ProcResourceIdx, PI->Cycles,
+ NextCycle, PI->StartAtCycle);
if (RCycle > NextCycle)
NextCycle = RCycle;
}
@@ -2708,27 +2699,27 @@ void SchedBoundary::bumpNode(SUnit *SU) {
if (SchedModel && SchedModel->enableIntervals()) {
unsigned ReservedUntil, InstanceIdx;
- std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
- SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
+ std::tie(ReservedUntil, InstanceIdx) =
+ getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
if (isTop()) {
ReservedResourceSegments[InstanceIdx].add(
ResourceSegments::getResourceIntervalTop(
- NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
+ NextCycle, PI->StartAtCycle, PI->Cycles),
MIResourceCutOff);
} else {
ReservedResourceSegments[InstanceIdx].add(
ResourceSegments::getResourceIntervalBottom(
- NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
+ NextCycle, PI->StartAtCycle, PI->Cycles),
MIResourceCutOff);
}
} else {
unsigned ReservedUntil, InstanceIdx;
- std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
- SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
+ std::tie(ReservedUntil, InstanceIdx) =
+ getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
if (isTop()) {
ReservedCycles[InstanceIdx] =
- std::max(ReservedUntil, NextCycle + PI->ReleaseAtCycle);
+ std::max(ReservedUntil, NextCycle + PI->Cycles);
} else
ReservedCycles[InstanceIdx] = NextCycle;
}
@@ -2926,9 +2917,9 @@ initResourceDelta(const ScheduleDAGMI *DAG,
PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
if (PI->ProcResourceIdx == Policy.ReduceResIdx)
- ResDelta.CritResources += PI->ReleaseAtCycle;
+ ResDelta.CritResources += PI->Cycles;
if (PI->ProcResourceIdx == Policy.DemandResIdx)
- ResDelta.DemandedResources += PI->ReleaseAtCycle;
+ ResDelta.DemandedResources += PI->Cycles;
}
}
@@ -4256,7 +4247,7 @@ static bool sortIntervals(const ResourceSegments::IntervalTy &A,
}
unsigned ResourceSegments::getFirstAvailableAt(
- unsigned CurrCycle, unsigned AcquireAtCycle, unsigned Cycle,
+ unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
std::function<ResourceSegments::IntervalTy(unsigned, unsigned, unsigned)>
IntervalBuilder) const {
assert(std::is_sorted(std::begin(_Intervals), std::end(_Intervals),
@@ -4264,7 +4255,7 @@ unsigned ResourceSegments::getFirstAvailableAt(
"Cannot execute on an un-sorted set of intervals.");
unsigned RetCycle = CurrCycle;
ResourceSegments::IntervalTy NewInterval =
- IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
+ IntervalBuilder(RetCycle, StartAtCycle, Cycle);
for (auto &Interval : _Intervals) {
if (!intersects(NewInterval, Interval))
continue;
@@ -4274,7 +4265,7 @@ unsigned ResourceSegments::getFirstAvailableAt(
assert(Interval.second > NewInterval.first &&
"Invalid intervals configuration.");
RetCycle += (unsigned)Interval.second - (unsigned)NewInterval.first;
- NewInterval = IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
+ NewInterval = IntervalBuilder(RetCycle, StartAtCycle, Cycle);
}
return RetCycle;
}
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index 3e6f36fe936fff..4f66f2e672d185 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -71,7 +71,7 @@ bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
Loops = &getAnalysis<MachineLoopInfo>();
SchedModel.init(&ST);
BlockInfo.resize(MF->getNumBlockIDs());
- ProcReleaseAtCycles.resize(MF->getNumBlockIDs() *
+ ProcResourceCycles.resize(MF->getNumBlockIDs() *
SchedModel.getNumProcResourceKinds());
return false;
}
@@ -126,7 +126,7 @@ MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
assert(PI->ProcResourceIdx < PRKinds && "Bad processor resource kind");
- PRCycles[PI->ProcResourceIdx] += PI->ReleaseAtCycle;
+ PRCycles[PI->ProcResourceIdx] += PI->Cycles;
}
}
FBI->InstrCount = InstrCount;
@@ -134,19 +134,19 @@ MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
// Scale the resource cycles so they are comparable.
unsigned PROffset = MBB->getNumber() * PRKinds;
for (unsigned K = 0; K != PRKinds; ++K)
- ProcReleaseAtCycles[PROffset + K] =
+ ProcResourceCycles[PROffset + K] =
PRCycles[K] * SchedModel.getResourceFactor(K);
return FBI;
}
ArrayRef<unsigned>
-MachineTraceMetrics::getProcReleaseAtCycles(unsigned MBBNum) const {
+MachineTraceMetrics::getProcResourceCycles(unsigned MBBNum) const {
assert(BlockInfo[MBBNum].hasResources() &&
- "getResources() must be called before getProcReleaseAtCycles()");
+ "getResources() must be called before getProcResourceCycles()");
unsigned PRKinds = SchedModel.getNumProcResourceKinds();
- assert((MBBNum+1) * PRKinds <= ProcReleaseAtCycles.size());
- return ArrayRef(ProcReleaseAtCycles.data() + MBBNum * PRKinds, PRKinds);
+ assert((MBBNum+1) * PRKinds <= ProcResourceCycles.size());
+ return ArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
}
//===----------------------------------------------------------------------===//
@@ -197,7 +197,7 @@ computeDepthResources(const MachineBasicBlock *MBB) {
// Compute per-resource depths.
ArrayRef<unsigned> PredPRDepths = getProcResourceDepths(PredNum);
- ArrayRef<unsigned> PredPRCycles = MTM.getProcReleaseAtCycles(PredNum);
+ ArrayRef<unsigned> PredPRCycles = MTM.getProcResourceCycles(PredNum);
for (unsigned K = 0; K != PRKinds; ++K)
ProcResourceDepths[PROffset + K] = PredPRDepths[K] + PredPRCycles[K];
}
@@ -212,7 +212,7 @@ computeHeightResources(const MachineBasicBlock *MBB) {
// Compute resources for the current block.
TBI->InstrHeight = MTM.getResources(MBB)->InstrCount;
- ArrayRef<unsigned> PRCycles = MTM.getProcReleaseAtCycles(MBB->getNumber());
+ ArrayRef<unsigned> PRCycles = MTM.getProcResourceCycles(MBB->getNumber());
// The trace tail is done.
if (!TBI->Succ) {
@@ -1204,7 +1204,7 @@ unsigned MachineTraceMetrics::Trace::getResourceDepth(bool Bottom) const {
unsigned PRMax = 0;
ArrayRef<unsigned> PRDepths = TE.getProcResourceDepths(getBlockNum());
if (Bottom) {
- ArrayRef<unsigned> PRCycles = TE.MTM.getProcReleaseAtCycles(getBlockNum());
+ ArrayRef<unsigned> PRCycles = TE.MTM.getProcResourceCycles(getBlockNum());
for (unsigned K = 0; K != PRDepths.size(); ++K)
PRMax = std::max(PRMax, PRDepths[K] + PRCycles[K]);
} else {
@@ -1248,8 +1248,8 @@ unsigned MachineTraceMetrics::Trace::getResourceLength(
PI != PE; ++PI) {
if (PI->ProcResourceIdx != ResourceIdx)
continue;
- Cycles += (PI->ReleaseAtCycle *
- TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
+ Cycles +=
+ (PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
}
}
return Cycles;
@@ -1258,7 +1258,7 @@ unsigned MachineTraceMetrics::Trace::getResourceLength(
for (unsigned K = 0; K != PRDepths.size(); ++K) {
unsigned PRCycles = PRDepths[K] + PRHeights[K];
for (const MachineBasicBlock *MBB : Extrablocks)
- PRCycles += TE.MTM.getProcReleaseAtCycles(MBB->getNumber())[K];
+ PRCycles += TE.MTM.getProcResourceCycles(MBB->getNumber())[K];
PRCycles += extraCycles(ExtraInstrs, K);
PRCycles -= extraCycles(RemoveInstrs, K);
PRMax = std::max(PRMax, PRCycles);
diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp
index 990a693559a777..5a893b803fd07b 100644
--- a/llvm/lib/MC/MCSchedule.cpp
+++ b/llvm/lib/MC/MCSchedule.cpp
@@ -94,10 +94,10 @@ MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
for (; I != E; ++I) {
- if (!I->ReleaseAtCycle)
+ if (!I->Cycles)
continue;
unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
- double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
+ double Temp = NumUnits * 1.0 / I->Cycles;
Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
}
if (Throughput)
diff --git a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
index 8d99695f4c29e5..393548dd5bd378 100644
--- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
+++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
@@ -346,7 +346,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const {
void ResourceManager::issueInstruction(
const InstrDesc &Desc,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes) {
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes) {
for (const std::pair<uint64_t, ResourceUsage> &R : Desc.Resources) {
const CycleSegment &CS = R.second.CS;
if (!CS.size()) {
@@ -359,8 +359,8 @@ void ResourceManager::issueInstruction(
ResourceRef Pipe = selectPipe(R.first);
use(Pipe);
BusyResources[Pipe] += CS.size();
- Pipes.emplace_back(std::pair<ResourceRef, ReleaseAtCycles>(
- Pipe, ReleaseAtCycles(CS.size())));
+ Pipes.emplace_back(std::pair<ResourceRef, ResourceCycles>(
+ Pipe, ResourceCycles(CS.size())));
} else {
assert((llvm::popcount(R.first) > 1) && "Expected a group!");
// Mark this group as reserved.
diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
index a9bbf697991986..31ea751f1c44c7 100644
--- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
+++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
@@ -69,7 +69,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
void Scheduler::issueInstructionImpl(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources) {
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources) {
Instruction *IS = IR.getInstruction();
const InstrDesc &D = IS->getDesc();
@@ -98,7 +98,7 @@ void Scheduler::issueInstructionImpl(
// Release the buffered resources and issue the instruction.
void Scheduler::issueInstruction(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources,
+ SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources,
SmallVectorImpl<InstRef> &PendingInstructions,
SmallVectorImpl<InstRef> &ReadyInstructions) {
const Instruction &Inst = *IR.getInstruction();
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp
index 1a82e45763a267..bddd370ea44859 100644
--- a/llvm/lib/MCA/InstrBuilder.cpp
+++ b/llvm/lib/MCA/InstrBuilder.cpp
@@ -69,7 +69,7 @@ static void initializeUsedResources(InstrDesc &ID,
for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) {
const MCWriteProcResEntry *PRE = STI.getWriteProcResBegin(&SCDesc) + I;
const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);
- if (!PRE->ReleaseAtCycle) {
+ if (!PRE->Cycles) {
#ifndef NDEBUG
WithColor::warning()
<< "Ignoring invalid write of zero cycles on processor resource "
@@ -89,11 +89,11 @@ static void initializeUsedResources(InstrDesc &ID,
AllInOrderResources &= (PR.BufferSize <= 1);
}
- CycleSegment RCy(0, PRE->ReleaseAtCycle, false);
+ CycleSegment RCy(0, PRE->Cycles, false);
Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy)));
if (PR.SuperIdx) {
uint64_t Super = ProcResourceMasks[PR.SuperIdx];
- SuperResources[Super] += PRE->ReleaseAtCycle;
+ SuperResources[Super] += PRE->Cycles;
}
}
@@ -156,7 +156,7 @@ static void initializeUsedResources(InstrDesc &ID,
// is reserved. For example (on target x86; cpu Haswell):
//
// SchedWriteRes<[HWPort0, HWPort1, HWPort01]> {
- // let ReleaseAtCycles = [2, 2, 3];
+ // let ResourceCycles = [2, 2, 3];
// }
//
// This means:
diff --git a/llvm/lib/MCA/Stages/ExecuteStage.cpp b/llvm/lib/MCA/Stages/ExecuteStage.cpp
index 7714d4ff8aedea..6d36c4aa353322 100644
--- a/llvm/lib/MCA/Stages/ExecuteStage.cpp
+++ b/llvm/lib/MCA/Stages/ExecuteStage.cpp
@@ -196,7 +196,7 @@ Error ExecuteStage::execute(InstRef &IR) {
// Reserve a slot in each buffered resource. Also, mark units with
// BufferSize=0 as reserved. Resources with a buffer size of zero will only
- // be released after MCIS is issued, and all the ReleaseAtCycles for those
+ // be released after MCIS is issued, and all the ResourceCycles for those
// units have been consumed.
bool IsReadyInstruction = HWS.dispatch(IR);
const Instruction &Inst = *IR.getInstruction();
diff --git a/llvm/lib/MCA/Stages/InstructionTables.cpp b/llvm/lib/MCA/Stages/InstructionTables.cpp
index 937cc7da8de724..a842b52dcd3901 100644
--- a/llvm/lib/MCA/Stages/InstructionTables.cpp
+++ b/llvm/lib/MCA/Stages/InstructionTables.cpp
@@ -38,7 +38,7 @@ Error InstructionTables::execute(InstRef &IR) {
for (unsigned I = 0, E = NumUnits; I < E; ++I) {
ResourceRef ResourceUnit = std::make_pair(Index, 1U << I);
UsedResources.emplace_back(
- std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits)));
+ std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits)));
}
continue;
}
@@ -53,8 +53,7 @@ Error InstructionTables::execute(InstRef &IR) {
for (unsigned I2 = 0, E2 = SubUnit.NumUnits; I2 < E2; ++I2) {
ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2);
UsedResources.emplace_back(std::make_pair(
- ResourceUnit,
- ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits)));
+ ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits)));
}
}
}
diff --git a/llvm/lib/MCA/Support.cpp b/llvm/lib/MCA/Support.cpp
index f8b8a2d129c1ce..517738c959fc74 100644
--- a/llvm/lib/MCA/Support.cpp
+++ b/llvm/lib/MCA/Support.cpp
@@ -21,7 +21,7 @@ namespace mca {
#define DEBUG_TYPE "llvm-mca"
-ReleaseAtCycles &ReleaseAtCycles::operator+=(const ReleaseAtCycles &RHS) {
+ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) {
if (Denominator == RHS.Denominator)
Numerator += RHS.Numerator;
else {
@@ -92,18 +92,18 @@ double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
// The number of available resource units affects the resource pressure
// distribution, as well as how many blocks can be executed every cycle.
for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
- unsigned ReleaseAtCycles = ProcResourceUsage[I];
- if (!ReleaseAtCycles)
+ unsigned ResourceCycles = ProcResourceUsage[I];
+ if (!ResourceCycles)
continue;
const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
- double Throughput = static_cast<double>(ReleaseAtCycles) / MCDesc.NumUnits;
+ double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits;
Max = std::max(Max, Throughput);
}
// The block reciprocal throughput is computed as the MAX of:
// - (NumMicroOps / DispatchWidth)
- // - (NumUnits / ReleaseAtCycles) for every consumed processor resource.
+ // - (NumUnits / ResourceCycles) for every consumed processor resource.
return Max;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index fab2cda8780755..2526fe3041909e 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -74,14 +74,14 @@ def : WriteRes<WriteIS, [CortexA510UnitALU]> { let Latency = 2; } // Shift/S
// MAC
def : WriteRes<WriteIM32, [CortexA510UnitMAC]> { let Latency = 3; } // 32-bit Multiply
-def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ReleaseAtCycles = [2];} // 64-bit Multiply
+def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ResourceCycles = [2];} // 64-bit Multiply
// Div
def : WriteRes<WriteID32, [CortexA510UnitDiv]> {
- let Latency = 8; let ReleaseAtCycles = [8];
+ let Latency = 8; let ResourceCycles = [8];
}
def : WriteRes<WriteID64, [CortexA510UnitDiv]> {
- let Latency = 16; let ReleaseAtCycles = [16];
+ let Latency = 16; let ResourceCycles = [16];
}
//===----------------------------------------------------------------------===//
@@ -94,7 +94,7 @@ class CortexA510Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {
class CortexA510MCWrite<int n, int m, ProcResourceKind res> : SchedWriteRes<[res]> {
let Latency = n;
- let ReleaseAtCycles = [m];
+ let ResourceCycles = [m];
let BeginGroup = 1;
}
@@ -127,15 +127,15 @@ def : WriteRes<WriteLDHi, [CortexA510UnitLd]> { let Latency = 2; }
def CortexA510WriteVLD1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteVLD1SI : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; let SingleIssue = 1; }
def CortexA510WriteVLD2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 4;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def CortexA510WriteVLD3 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA510WriteVLD4 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def CortexA510WriteVLD6 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA510WriteVLD8 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def CortexA510WriteLDP1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteLDP2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
@@ -154,14 +154,14 @@ def : WriteRes<WriteSTX, [CortexA510UnitLdSt]> { let Latency = 3; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [CortexA510UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [2];}
+ let ResourceCycles = [2];}
def CortexA510WriteVST1 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 4; }
def CortexA510WriteVST2 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def CortexA510WriteVST3 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA510WriteVST4 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@@ -183,7 +183,7 @@ def : WriteRes<WriteFImm, [CortexA510UnitVALU]> { let Latency = 3; }
class CortexA510VSt<int n> : SchedWriteRes<[CortexA510UnitLdSt]> {
let RetireOOO = 1;
- let ReleaseAtCycles = [n];
+ let ResourceCycles = [n];
}
def CortexA510VSt0 : SchedWriteRes<[CortexA510UnitLdSt]> {
@@ -202,20 +202,20 @@ def : WriteRes<WriteFMul, [CortexA510UnitVMAC]> { let Latency = 4; }
let RetireOOO = 1 in {
def : WriteRes<WriteFDiv, [CortexA510UnitVMC]> { let Latency = 22;
- let ReleaseAtCycles = [29]; }
+ let ResourceCycles = [29]; }
def CortexA510WriteVMAC : SchedWriteRes<[CortexA510UnitVMAC]> { let Latency = 4; }
def CortexA510WriteFDivHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def CortexA510WriteFDivSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 13;
- let ReleaseAtCycles = [10]; }
+ let ResourceCycles = [10]; }
def CortexA510WriteFDivDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
def CortexA510WriteFSqrtHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def CortexA510WriteFSqrtSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def CortexA510WriteFSqrtDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
}
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index 67e2b07692509a..e378b043d37e66 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -83,16 +83,16 @@ def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
// May model this more carefully in the future. The remaining
// A53WriteVLD# types represent the 1-5 cycle issues explicitly.
def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
// Pre/Post Indexing - Performed as part of address generation which is already
// accounted for in the WriteST* latencies below
@@ -106,12 +106,12 @@ def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [2];}
+ let ResourceCycles = [2];}
def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@@ -134,16 +134,16 @@ def : WriteRes<WriteVq, [A53UnitFPALU]> { let Latency = 6; }
// FP Mul, Div, Sqrt
def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
- let ReleaseAtCycles = [29]; }
+ let ResourceCycles = [29]; }
def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
- let ReleaseAtCycles = [14]; }
+ let ResourceCycles = [14]; }
def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
- let ReleaseAtCycles = [29]; }
+ let ResourceCycles = [29]; }
def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
- let ReleaseAtCycles = [13]; }
+ let ResourceCycles = [13]; }
def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
- let ReleaseAtCycles = [28]; }
+ let ResourceCycles = [28]; }
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA55.td b/llvm/lib/Target/AArch64/AArch64SchedA55.td
index 533fb933026060..141cc6b79c8b86 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA55.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA55.td
@@ -76,10 +76,10 @@ def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit M
// Div
def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
- let Latency = 8; let ReleaseAtCycles = [8];
+ let Latency = 8; let ResourceCycles = [8];
}
def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
- let Latency = 8; let ReleaseAtCycles = [8];
+ let Latency = 8; let ResourceCycles = [8];
}
// Load
@@ -91,23 +91,23 @@ def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }
// below, choosing the median of 3 which makes the latency 6.
// An extra cycle is needed to get the swizzling right.
def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA55WriteVLD1 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; }
def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1; }
def CortexA55WriteVLD2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def CortexA55WriteVLD3 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA55WriteVLD4 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 7;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def CortexA55WriteVLD5 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def CortexA55WriteVLD6 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 9;
- let ReleaseAtCycles = [6]; }
+ let ResourceCycles = [6]; }
def CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;
- let ReleaseAtCycles = [8]; }
+ let ResourceCycles = [8]; }
def CortexA55WriteLDP1 : SchedWriteRes<[]> { let Latency = 4; }
def CortexA55WriteLDP2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5; }
@@ -126,14 +126,14 @@ def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
- let ReleaseAtCycles = [2];}
+ let ResourceCycles = [2];}
def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }
def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def CortexA55WriteVST3 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 6;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def CortexA55WriteVST4 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@@ -189,20 +189,20 @@ def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
let RetireOOO = 1 in {
def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;
- let ReleaseAtCycles = [29]; }
+ let ResourceCycles = [29]; }
def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }
def CortexA55WriteFDivHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def CortexA55WriteFDivSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 13;
- let ReleaseAtCycles = [10]; }
+ let ResourceCycles = [10]; }
def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
def CortexA55WriteFSqrtHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
}
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td b/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
index fd16e98bff8051..a4c090d439dbcc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
@@ -34,17 +34,17 @@ def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
- let ReleaseAtCycles = [17]; }
+ let ResourceCycles = [17]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
- let ReleaseAtCycles = [32]; }
+ let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
- let ReleaseAtCycles = [35]; }
+ let ResourceCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
@@ -63,7 +63,7 @@ def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
let Latency = 64;
let NumMicroOps = 2;
- let ReleaseAtCycles = [32, 32];
+ let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
@@ -160,7 +160,7 @@ def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
let Latency = 34;
let NumMicroOps = 2;
- let ReleaseAtCycles = [17, 17];
+ let ResourceCycles = [17, 17];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index f3e844dc5b270d..cb88eddc2b2280 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -672,13 +672,13 @@ def : WriteRes<WriteIS, [A64FXGI2456]> {
// Divide, W-form
def : WriteRes<WriteID32, [A64FXGI4]> {
let Latency = 39;
- let ReleaseAtCycles = [39];
+ let ResourceCycles = [39];
}
// Divide, X-form
def : WriteRes<WriteID64, [A64FXGI4]> {
let Latency = 23;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
}
// Multiply accumulate, W-form
@@ -1254,7 +1254,7 @@ def : InstRW<[A64FXWrite_STUR, ReadAdrBase],
// FP negate
def : WriteRes<WriteF, [A64FXGI03]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// FP arithmetic
@@ -1265,7 +1265,7 @@ def : InstRW<[A64FXWrite_4Cyc_GI03], (instrs FSUBDrr, FSUBHrr)>;
// FP compare
def : WriteRes<WriteFCmp, [A64FXGI03]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// FP Div, Sqrt
@@ -1327,21 +1327,21 @@ def : InstRW<[A64FXWrite_4Cyc_GI03], (instregex "^FCSEL")>;
// FP convert, from vec to gen reg
def : WriteRes<WriteFCvt, [A64FXGI03]> {
let Latency = 9;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// FP move, immed
// FP move, register
def : WriteRes<WriteFImm, [A64FXGI0]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// FP transfer, from gen to vec reg
// FP transfer, from vec to gen reg
def : WriteRes<WriteFCopy, [A64FXGI0]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_FMOV_GV], (instrs FMOVXDHighr)>;
@@ -2113,14 +2113,14 @@ def : InstRW<[A64FXWrite_None], (instregex "^SETFFR", "^MOVPRFX")>;
def A64FXWrite_FMAIndexed : SchedWriteRes<[A64FXGI03]> {
let Latency = 15;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_FMAIndexed], (instregex "^F(MLA|MLS|MUL)_ZZZI")>;
def A64FXWrite_ADR_LSL_Z : SchedWriteRes<[A64FXGI0]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_ADR_LSL_Z], (instregex "^ADR_LSL_Z")>;
@@ -2133,7 +2133,7 @@ def : InstRW<[A64FXWrite_ASRD], (instregex "^ASRD_Z")>;
def A64FXWrite_Reduction4CycB : SchedWriteRes<[A64FXGI03]> {
let Latency = 46;
let NumMicroOps = 10;
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
}
def : InstRW<[A64FXWrite_Reduction4CycB],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
@@ -2141,7 +2141,7 @@ def : InstRW<[A64FXWrite_Reduction4CycB],
def A64FXWrite_Reduction4CycH : SchedWriteRes<[A64FXGI03]> {
let Latency = 42;
let NumMicroOps = 9;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_Reduction4CycH],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
@@ -2149,7 +2149,7 @@ def : InstRW<[A64FXWrite_Reduction4CycH],
def A64FXWrite_Reduction4CycS : SchedWriteRes<[A64FXGI03]> {
let Latency = 38;
let NumMicroOps = 8;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def : InstRW<[A64FXWrite_Reduction4CycS],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
@@ -2157,7 +2157,7 @@ def : InstRW<[A64FXWrite_Reduction4CycS],
def A64FXWrite_Reduction4CycD : SchedWriteRes<[A64FXGI03]> {
let Latency = 34;
let NumMicroOps = 7;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_Reduction4CycD],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
@@ -2184,7 +2184,7 @@ def : InstRW<[A64FXWrite_CPYScalar], (instregex "^CPY_ZPmR")>;
def A64FXWrite_CTERM : SchedWriteRes<[A64FXGI24]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_CTERM], (instregex "^CTERM")>;
@@ -2202,42 +2202,42 @@ def : InstRW<[A64FXWrite_INCPVector], (instregex "^DECP_Z", "^INCP_Z")>;
def A64FXWrite_FADDVH : SchedWriteRes<[A64FXGI03]> {
let Latency = 75;
let NumMicroOps = 11;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def : InstRW<[A64FXWrite_FADDVH], (instrs FADDV_VPZ_H)>;
def A64FXWrite_FADDVS : SchedWriteRes<[A64FXGI03]> {
let Latency = 60;
let NumMicroOps = 9;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_FADDVS], (instrs FADDV_VPZ_S)>;
def A64FXWrite_FADDVD : SchedWriteRes<[A64FXGI03]> {
let Latency = 45;
let NumMicroOps = 7;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_FADDVD], (instrs FADDV_VPZ_D)>;
def A64FXWrite_FADDAH : SchedWriteRes<[A64FXGI03]> {
let Latency = 468;
let NumMicroOps = 63;
- let ReleaseAtCycles = [63];
+ let ResourceCycles = [63];
}
def : InstRW<[A64FXWrite_FADDAH], (instrs FADDA_VPZ_H)>;
def A64FXWrite_FADDAS : SchedWriteRes<[A64FXGI03]> {
let Latency = 228;
let NumMicroOps = 31;
- let ReleaseAtCycles = [31];
+ let ResourceCycles = [31];
}
def : InstRW<[A64FXWrite_FADDAS], (instrs FADDA_VPZ_S)>;
def A64FXWrite_FADDAD : SchedWriteRes<[A64FXGI03]> {
let Latency = 108;
let NumMicroOps = 15;
- let ReleaseAtCycles = [15];
+ let ResourceCycles = [15];
}
def : InstRW<[A64FXWrite_FADDAD], (instrs FADDA_VPZ_D)>;
@@ -2250,53 +2250,53 @@ def : InstRW<[A64FXWrite_FCADDZ], (instregex "^FCADD_Z")>;
def A64FXWrite_FCMLAZ : SchedWriteRes<[A64FXGI03]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_FCMLAZ], (instregex "^FCMLA_Z")>;
def A64FXWrite_FDIVH : SchedWriteRes<[A64FXGI0]> {
let Latency = 134;
- let ReleaseAtCycles = [134];
+ let ResourceCycles = [134];
}
def : InstRW<[A64FXWrite_FDIVH], (instregex "^F(DIVR?|SQRT)_Z.*_H")>;
def A64FXWrite_FDIVS : SchedWriteRes<[A64FXGI0]> {
let Latency = 98;
- let ReleaseAtCycles = [98];
+ let ResourceCycles = [98];
}
def : InstRW<[A64FXWrite_FDIVS], (instregex "^F(DIVR?|SQRT)_Z.*_S")>;
def A64FXWrite_FDIVD : SchedWriteRes<[A64FXGI0]> {
let Latency = 154;
- let ReleaseAtCycles = [154];
+ let ResourceCycles = [154];
}
def : InstRW<[A64FXWrite_FDIVD], (instregex "^F(DIVR?|SQRT)_Z.*_D")>;
def A64FXWrite_FMAXVH : SchedWriteRes<[A64FXGI03]> {
let Latency = 54;
let NumMicroOps = 11;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_H")>;
def A64FXWrite_FMAXVS : SchedWriteRes<[A64FXGI03]> {
let Latency = 44;
let NumMicroOps = 9;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_FMAXVS], (instregex "^F(MAX|MIN)(NM)?V_VPZ_S")>;
def A64FXWrite_FMAXVD : SchedWriteRes<[A64FXGI03]> {
let Latency = 34;
let NumMicroOps = 7;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_D")>;
def A64FXWrite_INDEX_RI_BH : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
let Latency = 17;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
}
def : InstRW<[A64FXWrite_INDEX_RI_BH], (instregex "^INDEX_(RI|IR)_[BH]")>;
@@ -2309,21 +2309,21 @@ def : InstRW<[A64FXWrite_INDEX_RI_SD], (instregex "^INDEX_(RI|IR)_[SD]")>;
def A64FXWrite_INDEX_II_BH : SchedWriteRes<[A64FXGI0]> {
let Latency = 13;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_INDEX_II_BH], (instregex "^INDEX_II_[BH]")>;
def A64FXWrite_INDEX_RR_BH : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI3]> {
let Latency = 17;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 2, 1];
+ let ResourceCycles = [2, 2, 1];
}
def : InstRW<[A64FXWrite_INDEX_RR_BH], (instregex "^INDEX_RR_[BH]")>;
def A64FXWrite_INDEX_RR_SD : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
let Latency = 17;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
def : InstRW<[A64FXWrite_INDEX_RR_SD], (instregex "^INDEX_RR_[SD]")>;
@@ -2339,28 +2339,28 @@ def : InstRW<[A64FXWrite_CLAST_R], (instregex "^LAST[AB]_R")>;
def A64FXWrite_GLD_S_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 19;
- let ReleaseAtCycles = [2, 4, 4];
+ let ResourceCycles = [2, 4, 4];
}
def : InstRW<[A64FXWrite_GLD_S_ZI],
(instregex "^GLD(FF)?1W_IMM", "^GLD(FF)?1S?[BHW]_S_IMM")>;
def A64FXWrite_GLD_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
- let ReleaseAtCycles = [1, 2, 2];
+ let ResourceCycles = [1, 2, 2];
}
def : InstRW<[A64FXWrite_GLD_D_ZI],
(instregex "^GLD(FF)?1D_IMM", "^GLD(FF)?1S?[BHW]_D_IMM")>;
def A64FXWrite_GLD_S_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 23;
- let ReleaseAtCycles = [2, 1, 4, 4];
+ let ResourceCycles = [2, 1, 4, 4];
}
def : InstRW<[A64FXWrite_GLD_S_RZ],
(instregex "^GLD(FF)?1W_[^DI]", "^GLD(FF)?1S?[BHW]_S_[^I]")>;
def A64FXWrite_GLD_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
- let ReleaseAtCycles = [1, 1, 2, 2];
+ let ResourceCycles = [1, 1, 2, 2];
}
def : InstRW<[A64FXWrite_GLD_D_RZ],
(instregex "^GLD(FF)?1D_[^I]", "^GLD(FF)?1D$", "^GLD(FF)?1S?[BHW]_D_[^I]",
@@ -2369,63 +2369,63 @@ def : InstRW<[A64FXWrite_GLD_D_RZ],
def A64FXWrite_LD2_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
def A64FXWrite_LD2_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_LD2_WD_IMM], (instregex "^LD2[WD]_IMM")>;
def A64FXWrite_LD2_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_LD2_WD], (instregex "^LD2[WD]$")>;
def A64FXWrite_LD3_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 4;
- let ReleaseAtCycles = [13];
+ let ResourceCycles = [13];
}
def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>;
def A64FXWrite_LD3_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_LD3_WD_IMM], (instregex "^LD3[WD]_IMM")>;
def A64FXWrite_LD3_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : InstRW<[A64FXWrite_LD3_WD], (instregex "^LD3[WD]$")>;
def A64FXWrite_LD4_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 5;
- let ReleaseAtCycles = [17];
+ let ResourceCycles = [17];
}
def : InstRW<[A64FXWrite_LD4_BH], (instregex "^LD4[BH]")>;
def A64FXWrite_LD4_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : InstRW<[A64FXWrite_LD4_WD_IMM], (instregex "^LD4[WD]_IMM")>;
def A64FXWrite_LD4_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 5;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
}
def : InstRW<[A64FXWrite_LD4_WD], (instregex "^LD4[WD]$")>;
@@ -2434,34 +2434,34 @@ def A64FXWrite_PRF : SchedWriteRes<[A64FXGI56]> {
def : InstRW<[A64FXWrite_PRF], (instregex "^PRF._PR")>;
def A64FXWrite_PRF_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
- let ReleaseAtCycles = [2, 1, 4];
+ let ResourceCycles = [2, 1, 4];
}
def : InstRW<[A64FXWrite_PRF_W_RZ], (instregex "^PRF._S_[^P]")>;
def A64FXWrite_PRF_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
- let ReleaseAtCycles = [2, 4];
+ let ResourceCycles = [2, 4];
}
def : InstRW<[A64FXWrite_PRF_W_ZI], (instregex "^PRF._S_PZI")>;
def A64FXWrite_PRF_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
}
def : InstRW<[A64FXWrite_PRF_D_RZ], (instregex "^PRF._D_[^P]")>;
def A64FXWrite_PRF_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[A64FXWrite_PRF_D_ZI], (instregex "^PRF._D_PZI")>;
def A64FXWrite_SDIV_S : SchedWriteRes<[A64FXGI0]> {
let Latency = 114;
- let ReleaseAtCycles = [114];
+ let ResourceCycles = [114];
}
def : InstRW<[A64FXWrite_SDIV_S], (instregex "^[SU]DIVR?.*_S")>;
def A64FXWrite_SDIV_D : SchedWriteRes<[A64FXGI0]> {
let Latency = 178;
- let ReleaseAtCycles = [178];
+ let ResourceCycles = [178];
}
def : InstRW<[A64FXWrite_SDIV_D], (instregex "^[SU]DIVR?.*_D")>;
@@ -2473,14 +2473,14 @@ def : InstRW<[A64FXWrite_SDOT_I], (instregex "^[SU]DOT_ZZZI")>;
def A64FXWrite_SQINC_Scalar : SchedWriteRes<[A64FXGI24]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_SQINC_Scalar], (instregex "^[SU]Q(INC|DEC)[BHWD]_[WX]")>;
def A64FXWrite_SQINCP_X : SchedWriteRes<[A64FXGI24, A64FXGI3]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
}
def : InstRW<[A64FXWrite_SQINCP_X], (instregex "^[SU]Q(INC|DEC)P_[WX]")>;
@@ -2497,7 +2497,7 @@ def : InstRW<[A64FXWrite_ST1], (instregex "^ST(NT)?1[BHWD]")>;
def A64FXWrite_SST1_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
let NumMicroOps = 8;
- let ReleaseAtCycles = [8, 8, 8, 8];
+ let ResourceCycles = [8, 8, 8, 8];
}
def : InstRW<[A64FXWrite_SST1_W_RZ],
(instregex "^SST1[BH]_S(_[^I]|$)", "^SST1W(_[^ID]|$)")>;
@@ -2505,7 +2505,7 @@ def : InstRW<[A64FXWrite_SST1_W_RZ],
def A64FXWrite_SST1_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4, 4, 4, 4];
+ let ResourceCycles = [4, 4, 4, 4];
}
def : InstRW<[A64FXWrite_SST1_D_RZ],
(instregex "^SST1[BHW]_D(_[^I]|$)", "^SST1D(_[^I]|$)")>;
@@ -2513,7 +2513,7 @@ def : InstRW<[A64FXWrite_SST1_D_RZ],
def A64FXWrite_SST1_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
let NumMicroOps = 8;
- let ReleaseAtCycles = [12, 8, 8];
+ let ResourceCycles = [12, 8, 8];
}
def : InstRW<[A64FXWrite_SST1_W_ZI],
(instregex "^SST1[BH]_S_I", "^SST1W_I")>;
@@ -2521,7 +2521,7 @@ def : InstRW<[A64FXWrite_SST1_W_ZI],
def A64FXWrite_SST1_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4, 4, 4];
+ let ResourceCycles = [4, 4, 4];
}
def : InstRW<[A64FXWrite_SST1_D_ZI],
(instregex "^SST1[BHW]_D_I", "^SST1D_I")>;
@@ -2529,63 +2529,63 @@ def : InstRW<[A64FXWrite_SST1_D_ZI],
def A64FXWrite_ST2_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [8, 9];
+ let ResourceCycles = [8, 9];
}
def : InstRW<[A64FXWrite_ST2_BH], (instregex "^ST2[BH]")>;
def A64FXWrite_ST2_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
}
def : InstRW<[A64FXWrite_ST2_WD_RI], (instregex "^ST2[WD]$")>;
def A64FXWrite_ST2_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 3];
+ let ResourceCycles = [2, 3];
}
def : InstRW<[A64FXWrite_ST2_WD_RR], (instregex "^ST2[WD]_I")>;
def A64FXWrite_ST3_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 4;
- let ReleaseAtCycles = [12, 13];
+ let ResourceCycles = [12, 13];
}
def : InstRW<[A64FXWrite_ST3_BH], (instregex "^ST3[BH]")>;
def A64FXWrite_ST3_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3, 3];
+ let ResourceCycles = [3, 3];
}
def : InstRW<[A64FXWrite_ST3_WD_RI], (instregex "^ST3[WD]$")>;
def A64FXWrite_ST3_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3, 4];
+ let ResourceCycles = [3, 4];
}
def : InstRW<[A64FXWrite_ST3_WD_RR], (instregex "^ST3[WD]_I")>;
def A64FXWrite_ST4_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 5;
- let ReleaseAtCycles = [16, 17];
+ let ResourceCycles = [16, 17];
}
def : InstRW<[A64FXWrite_ST4_BH], (instregex "^ST4[BH]")>;
def A64FXWrite_ST4_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4, 4];
+ let ResourceCycles = [4, 4];
}
def : InstRW<[A64FXWrite_ST4_WD_RI], (instregex "^ST4[WD]$")>;
def A64FXWrite_ST4_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 5;
- let ReleaseAtCycles = [4, 5];
+ let ResourceCycles = [4, 5];
}
def : InstRW<[A64FXWrite_ST4_WD_RR], (instregex "^ST4[WD]_I")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 1ef3a2a063382d..e2d916954060de 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -158,7 +158,7 @@ def : WriteRes<WriteI, [CyUnitI]>;
// EXAMPLE: ADDrs Xn, Xm LSL #imm
def : WriteRes<WriteISReg, [CyUnitIS]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// ADD with extended register operand is the same as shifted reg operand.
@@ -166,7 +166,7 @@ def : WriteRes<WriteISReg, [CyUnitIS]> {
// EXAMPLE: ADDXre Xn, Xm, UXTB #1
def : WriteRes<WriteIEReg, [CyUnitIS]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// Variable shift and bitfield operations.
@@ -209,14 +209,14 @@ def : WriteRes<WriteIM64, [CyUnitIM]> {
// SDIVW,UDIVW
def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
let Latency = 10;
- let ReleaseAtCycles = [2, 10];
+ let ResourceCycles = [2, 10];
}
// 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
// The ID pipe is consumed for 2 cycles: issue and writeback.
// SDIVX,UDIVX
def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
let Latency = 13;
- let ReleaseAtCycles = [2, 13];
+ let ResourceCycles = [2, 13];
}
//---
@@ -555,7 +555,7 @@ def : InstRW<[CyWritePMUL], (instregex "PMULv", "PMULLv")>;
// TODO: Specialize FSQRT for longer latency.
def : WriteRes<WriteFDiv, [CyUnitVD, CyUnitFloatDiv]> {
let Latency = 17;
- let ReleaseAtCycles = [2, 17];
+ let ResourceCycles = [2, 17];
}
def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 2127a34a58d513..728eecfa645e14 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -115,7 +115,7 @@ def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M3WriteAB : SchedWriteRes<[M3UnitALU,
M3UnitC]> { let Latency = 1;
let NumMicroOps = 2; }
@@ -207,13 +207,13 @@ def : SchedAlias<WriteImm, M3WriteA1>;
// Divide and multiply instructions.
def : WriteRes<WriteID32, [M3UnitC,
M3UnitD]> { let Latency = 12;
- let ReleaseAtCycles = [1, 12]; }
+ let ResourceCycles = [1, 12]; }
def : WriteRes<WriteID64, [M3UnitC,
M3UnitD]> { let Latency = 21;
- let ReleaseAtCycles = [1, 21]; }
+ let ResourceCycles = [1, 21]; }
def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
// Miscellaneous instructions.
def : SchedAlias<WriteExtr, M3WriteAY>;
@@ -238,7 +238,7 @@ def : SchedAlias<WriteSTIdx, M3WriteSB>;
def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; }
def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; }
def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
+ let ResourceCycles = [12]; }
def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; }
// FP miscellaneous instructions.
@@ -302,19 +302,19 @@ def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF,
def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0,
M3UnitFDIV1]> { let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [8, 8]; }
+ let ResourceCycles = [8, 8]; }
def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0,
M3UnitFDIV1]> { let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [13, 13]; }
+ let ResourceCycles = [13, 13]; }
def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 18;
let NumMicroOps = 2;
- let ReleaseAtCycles = [19, 19]; }
+ let ResourceCycles = [19, 19]; }
def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 25;
let NumMicroOps = 2;
- let ReleaseAtCycles = [26, 26]; }
+ let ResourceCycles = [26, 26]; }
def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC,
M3UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2; }
@@ -325,16 +325,16 @@ def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; }
def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7;
- let ReleaseAtCycles = [8]; }
+ let ResourceCycles = [8]; }
def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [13]; }
+ let ResourceCycles = [13]; }
def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; }
def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; }
def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; }
def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25;
- let ReleaseAtCycles = [26]; }
+ let ResourceCycles = [26]; }
def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; }
def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
@@ -363,50 +363,50 @@ def M3WriteVLDC : SchedWriteRes<[M3UnitL,
def M3WriteVLDD : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 1]; }
+ let ResourceCycles = [2, 1]; }
def M3WriteVLDE : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 1]; }
+ let ResourceCycles = [2, 1]; }
def M3WriteVLDF : SchedWriteRes<[M3UnitL,
M3UnitL]> { let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [5, 5]; }
+ let ResourceCycles = [5, 5]; }
def M3WriteVLDG : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1, 1]; }
+ let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDH : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1, 1]; }
+ let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDI : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [6, 6, 6]; }
+ let ResourceCycles = [6, 6, 6]; }
def M3WriteVLDJ : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2, 1, 1, 1]; }
+ let ResourceCycles = [2, 1, 1, 1]; }
def M3WriteVLDK : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [4, 1, 1, 1, 1]; }
+ let ResourceCycles = [4, 1, 1, 1, 1]; }
def M3WriteVLDL : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 5;
- let ReleaseAtCycles = [6, 1, 1, 6, 1]; }
+ let ResourceCycles = [6, 1, 1, 6, 1]; }
def M3WriteVLDM : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
@@ -414,13 +414,13 @@ def M3WriteVLDM : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 6;
- let ReleaseAtCycles = [6, 1, 1, 6, 1, 1]; }
+ let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
def M3WriteVLDN : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 14;
let NumMicroOps = 4;
- let ReleaseAtCycles = [6, 6, 6, 6]; }
+ let ResourceCycles = [6, 6, 6, 6]; }
def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
@@ -429,7 +429,7 @@ def M3WriteVSTD : SchedWriteRes<[M3UnitS,
M3UnitS,
M3UnitFST]> { let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 1, 3]; }
def M3WriteVSTE : SchedWriteRes<[M3UnitS,
M3UnitFST,
M3UnitS,
@@ -437,7 +437,7 @@ def M3WriteVSTE : SchedWriteRes<[M3UnitS,
M3UnitS,
M3UnitFST]> { let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1, 3, 1, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -446,7 +446,7 @@ def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 15;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -457,14 +457,14 @@ def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 16;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
def M3WriteVSTH : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 14;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1, 3, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 3, 1, 3]; }
def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@@ -475,7 +475,7 @@ def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 17;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
+ let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
// Special cases.
def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; }
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index 83cf56088d4ced..66e1c0b9ced12a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -142,7 +142,7 @@ def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M4WriteAB : SchedWriteRes<[M4UnitALU,
M4UnitC]> { let Latency = 2;
let NumMicroOps = 2; }
@@ -176,12 +176,12 @@ def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>
def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
+ let ResourceCycles = [12]; }
def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
- let ReleaseAtCycles = [21]; }
+ let ResourceCycles = [21]; }
def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
@@ -265,22 +265,22 @@ def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0,
let NumMicroOps = 1; }
def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV,
M4UnitFDIV]> { let Latency = 7;
- let ReleaseAtCycles = [6, 6]; }
+ let ResourceCycles = [6, 6]; }
def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH,
M4UnitFDIVH]> { let Latency = 7;
- let ReleaseAtCycles = [6, 6]; }
+ let ResourceCycles = [6, 6]; }
def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV,
M4UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [9, 9]; }
+ let ResourceCycles = [9, 9]; }
def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR,
M4UnitFSQR]> { let Latency = 8;
- let ReleaseAtCycles = [7, 7]; }
+ let ResourceCycles = [7, 7]; }
def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH,
M4UnitFSQRH]> { let Latency = 7;
- let ReleaseAtCycles = [6, 6]; }
+ let ResourceCycles = [6, 6]; }
def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR,
M4UnitFSQR]> { let Latency = 12;
- let ReleaseAtCycles = [9, 9]; }
+ let ResourceCycles = [9, 9]; }
def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
SchedVar<NoSchedPred, [M4WriteNEONN]>]>;
@@ -298,11 +298,11 @@ def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7;
- let ReleaseAtCycles = [6]; }
+ let ResourceCycles = [6]; }
def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
- let ReleaseAtCycles = [6]; }
+ let ResourceCycles = [6]; }
def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
@@ -312,11 +312,11 @@ def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; }
def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
- let ReleaseAtCycles = [6]; }
+ let ResourceCycles = [6]; }
def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; }
def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
@@ -339,16 +339,16 @@ def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; }
def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; }
def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; }
def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; }
@@ -370,41 +370,41 @@ def M4WriteVLDC : SchedWriteRes<[M4UnitL,
def M4WriteVLDD : SchedWriteRes<[M4UnitL,
M4UnitNSHF]> { let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 1]; }
+ let ResourceCycles = [2, 1]; }
def M4WriteVLDF : SchedWriteRes<[M4UnitL,
M4UnitL]> { let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [3, 3]; }
+ let ResourceCycles = [3, 3]; }
def M4WriteVLDG : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1, 1]; }
+ let ResourceCycles = [2, 1, 1]; }
def M4WriteVLDI : SchedWriteRes<[M4UnitL,
M4UnitL,
M4UnitL]> { let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3, 3, 3]; }
+ let ResourceCycles = [3, 3, 3]; }
def M4WriteVLDJ : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3, 1, 1, 1]; }
+ let ResourceCycles = [3, 1, 1, 1]; }
def M4WriteVLDK : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [3, 1, 1, 1, 1]; }
+ let ResourceCycles = [3, 1, 1, 1, 1]; }
def M4WriteVLDL : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitL,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [3, 1, 1, 6, 1]; }
+ let ResourceCycles = [3, 1, 1, 6, 1]; }
def M4WriteVLDM : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
@@ -412,13 +412,13 @@ def M4WriteVLDM : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 6;
- let ReleaseAtCycles = [3, 1, 1, 3, 1, 1]; }
+ let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
def M4WriteVLDN : SchedWriteRes<[M4UnitL,
M4UnitL,
M4UnitL,
M4UnitL]> { let Latency = 14;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3, 3, 3, 3]; }
+ let ResourceCycles = [3, 3, 3, 3]; }
def M4WriteVST1 : SchedWriteRes<[M4UnitS,
M4UnitFST]> { let Latency = 1;
@@ -439,7 +439,7 @@ def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 2, 1, 2, 1]; }
def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
@@ -450,7 +450,7 @@ def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
@@ -464,7 +464,7 @@ def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
def M4WriteVSTJ : SchedWriteRes<[M4UnitA,
M4UnitS,
M4UnitFST,
@@ -482,7 +482,7 @@ def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
SchedVar<NoSchedPred, [WriteVST]>]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
index 85058af86decb5..a6405d4fc49cb8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -142,9 +142,9 @@ def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M5WriteAB : SchedWriteRes<[M5UnitAX,
M5UnitC,
M5UnitE]> { let Latency = 2;
@@ -194,12 +194,12 @@ def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>
def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
- let ReleaseAtCycles = [10]; }
+ let ResourceCycles = [10]; }
def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
- let ReleaseAtCycles = [16]; }
+ let ResourceCycles = [16]; }
def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
@@ -228,22 +228,22 @@ def M5WriteLFW : SchedWriteRes<[M5UnitAW,
M5UnitAW,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
+ let ResourceCycles = [1, 1, 1, 1, 15]; }
def M5WriteLFX : SchedWriteRes<[M5UnitAX,
M5UnitAX,
M5UnitAX,
M5UnitAX,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
+ let ResourceCycles = [1, 1, 1, 1, 15]; }
def M5WriteLGW : SchedWriteRes<[M5UnitAW,
M5UnitL]> { let Latency = 13;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1, 13]; }
+ let ResourceCycles = [1, 13]; }
def M5WriteLGX : SchedWriteRes<[M5UnitAX,
M5UnitL]> { let Latency = 13;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1, 13]; }
+ let ResourceCycles = [1, 13]; }
def M5WriteLH : SchedWriteRes<[]> { let Latency = 6;
let NumMicroOps = 0; }
def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
@@ -282,12 +282,12 @@ def M5WriteNEONK : SchedWriteRes<[M5UnitNSHF,
def M5WriteNEONN : SchedWriteRes<[M5UnitNMSC,
M5UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [7, 7]; }
+ let ResourceCycles = [7, 7]; }
def M5WriteNEONO : SchedWriteRes<[M5UnitNMSC,
M5UnitNMSC,
M5UnitNMSC]> { let Latency = 8;
let NumMicroOps = 3;
- let ReleaseAtCycles = [10, 10, 10]; }
+ let ResourceCycles = [10, 10, 10]; }
def M5WriteNEONP : SchedWriteRes<[M5UnitNSHF,
M5UnitS0,
M5UnitFCVT]> { let Latency = 7;
@@ -297,19 +297,19 @@ def M5WriteNEONQ : SchedWriteRes<[M5UnitNMSC,
let NumMicroOps = 1; }
def M5WriteNEONU : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 7;
- let ReleaseAtCycles = [4, 4]; }
+ let ResourceCycles = [4, 4]; }
def M5WriteNEONV : SchedWriteRes<[M5UnitFDIV,
M5UnitFDIV]> { let Latency = 7;
- let ReleaseAtCycles = [6, 6]; }
+ let ResourceCycles = [6, 6]; }
def M5WriteNEONW : SchedWriteRes<[M5UnitFDIV,
M5UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [9, 9]; }
+ let ResourceCycles = [9, 9]; }
def M5WriteNEONX : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 8;
- let ReleaseAtCycles = [5, 5]; }
+ let ResourceCycles = [5, 5]; }
def M5WriteNEONY : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 12;
- let ReleaseAtCycles = [9, 9]; }
+ let ResourceCycles = [9, 9]; }
def M5WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
SchedVar<NoSchedPred, [M5WriteNEONN]>]>;
@@ -330,24 +330,24 @@ def M5WriteFCVTC : SchedWriteRes<[M5UnitFCVT,
let NumMicroOps = 1; }
def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; }
def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; }
def M5WriteFMAC5 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 5; }
def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7;
- let ReleaseAtCycles = [4]; }
+ let ResourceCycles = [4]; }
def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12;
- let ReleaseAtCycles = [9]; }
+ let ResourceCycles = [9]; }
def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; }
def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; }
@@ -396,16 +396,16 @@ def M5WriteVLDC : SchedWriteRes<[M5UnitL,
def M5WriteVLDD : SchedWriteRes<[M5UnitL,
M5UnitNSHF]> { let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 1]; }
+ let ResourceCycles = [2, 1]; }
def M5WriteVLDF : SchedWriteRes<[M5UnitL,
M5UnitL]> { let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [6, 5]; }
+ let ResourceCycles = [6, 5]; }
def M5WriteVLDG : SchedWriteRes<[M5UnitL,
M5UnitNSHF,
M5UnitNSHF]> { let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1, 1]; }
+ let ResourceCycles = [2, 1, 1]; }
def M5WriteVLDI : SchedWriteRes<[M5UnitL,
M5UnitL,
M5UnitL]> { let Latency = 13;
@@ -439,7 +439,7 @@ def M5WriteVLDN : SchedWriteRes<[M5UnitL,
M5UnitL,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2, 2, 2, 2]; }
+ let ResourceCycles = [2, 2, 2, 2]; }
def M5WriteVST1 : SchedWriteRes<[M5UnitS,
M5UnitFST]> { let Latency = 1;
@@ -501,7 +501,7 @@ def M5WriteVSTI : SchedWriteRes<[M5UnitNSHF,
M5UnitS,
M5UnitFST]> { let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
def M5WriteVSTJ : SchedWriteRes<[M5UnitA,
M5UnitS0,
M5UnitFST]> { let Latency = 1;
@@ -517,7 +517,7 @@ def M5WriteVSTL : SchedWriteRes<[M5UnitNSHF,
M5UnitS,
M5UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
+ let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
def M5WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
SchedVar<NoSchedPred, [WriteVST]>]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
index 375e3652c9e878..d5788795c7a131 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
@@ -210,13 +210,13 @@ def FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> {
def FalkorWr_1X_1Z_8cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 8];
+ let ResourceCycles = [2, 8];
}
def FalkorWr_1X_1Z_11cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2, 11];
+ let ResourceCycles = [2, 11];
}
def FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
index 220bebc668ed50..d689b9fa9c068a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
@@ -84,13 +84,13 @@ def N1Write_1c_1I : SchedWriteRes<[N1UnitI]> { let Latency = 1; }
def N1Write_2c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 2; }
def N1Write_3c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 3; }
def N1Write_4c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 4;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def N1Write_5c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def N1Write_12c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 12;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def N1Write_20c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 20;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def N1Write_4c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 4; }
def N1Write_5c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 5; }
def N1Write_7c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 7; }
@@ -102,15 +102,15 @@ def N1Write_2c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 2; }
def N1Write_3c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 3; }
def N1Write_4c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }
def N1Write_7c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def N1Write_10c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 10;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def N1Write_13c10_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 13;
- let ReleaseAtCycles = [10]; }
+ let ResourceCycles = [10]; }
def N1Write_15c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 15;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def N1Write_17c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 17;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def N1Write_2c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 2; }
def N1Write_3c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 3; }
def N1Write_4c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index a6e28e653e33c1..6bb71f2ce23609 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -82,15 +82,15 @@ def N2Write_1cyc_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }
def N2Write_2cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 2; }
def N2Write_3cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 3; }
def N2Write_2cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def N2Write_3cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 3;
- let ReleaseAtCycles = [3]; }
+ let ResourceCycles = [3]; }
def N2Write_5cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 5;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def N2Write_12cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
+ let ResourceCycles = [12]; }
def N2Write_20cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def N2Write_4cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 4; }
def N2Write_6cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 6; }
def N2Write_2cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 2; }
@@ -102,7 +102,7 @@ def N2Write_2cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 2; }
def N2Write_3cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 3; }
def N2Write_4cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 4; }
def N2Write_7cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def N2Write_9cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 9; }
def N2Write_10cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 10; }
def N2Write_12cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 12; }
@@ -188,25 +188,25 @@ def N2Write_4cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
def N2Write_10cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [5, 5];
+ let ResourceCycles = [5, 5];
}
def N2Write_13cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 13;
let NumMicroOps = 2;
- let ReleaseAtCycles = [6, 7];
+ let ResourceCycles = [6, 7];
}
def N2Write_15cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 15;
let NumMicroOps = 2;
- let ReleaseAtCycles = [7, 8];
+ let ResourceCycles = [7, 8];
}
def N2Write_16cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 16;
let NumMicroOps = 2;
- let ReleaseAtCycles = [8, 8];
+ let ResourceCycles = [8, 8];
}
def N2Write_4cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 8792aa618ae057..571f290bbf839b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -111,9 +111,9 @@ def V1Write_2c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 2; }
def V1Write_3c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 3; }
def V1Write_5c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 5; }
def V1Write_12c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 12;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def V1Write_20c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 20;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def V1Write_2c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 2; }
def V1Write_3c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 3; }
def V1Write_4c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 4; }
@@ -123,17 +123,17 @@ def V1Write_3c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 3; }
def V1Write_4c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 4; }
def V1Write_6c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 6; }
def V1Write_10c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 10;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_12c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 12;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_13c10_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 13;
- let ReleaseAtCycles = [10]; }
+ let ResourceCycles = [10]; }
def V1Write_15c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 15;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_16c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 16;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_20c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 20;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_2c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 2; }
def V1Write_3c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }
def V1Write_4c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }
@@ -141,17 +141,17 @@ def V1Write_5c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }
def V1Write_3c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 3; }
def V1Write_4c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }
def V1Write_7c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_10c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 10;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_13c5_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
- let ReleaseAtCycles = [5]; }
+ let ResourceCycles = [5]; }
def V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
- let ReleaseAtCycles = [11]; }
+ let ResourceCycles = [11]; }
def V1Write_15c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 15;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_16c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 16;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V1Write_2c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 2; }
def V1Write_3c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 3; }
def V1Write_4c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 4; }
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index c7edc0a567524a..199ebc6ac650cf 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -102,9 +102,9 @@ def V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
def V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }
def V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }
def V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
+ let ResourceCycles = [12]; }
def V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }
def V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }
def V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }
@@ -113,7 +113,7 @@ def V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
def V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
def V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }
def V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
def V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }
def V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
@@ -124,26 +124,26 @@ def V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
def V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }
def V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
def V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
+ let ResourceCycles = [7]; }
def V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }
def V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }
def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
- let ReleaseAtCycles = [2]; }
+ let ResourceCycles = [2]; }
def V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;
- let ReleaseAtCycles = [11]; }
+ let ResourceCycles = [11]; }
def V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }
def V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }
def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
- let ReleaseAtCycles = [8]; }
+ let ResourceCycles = [8]; }
def V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }
def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
- let ReleaseAtCycles = [8]; }
+ let ResourceCycles = [8]; }
def V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }
def V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
def V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }
@@ -1054,19 +1054,19 @@ def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;
//===----------------------------------------------------------------------===//
// Define types with long resource cycles (rc)
-def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }
-def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }
-def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
-def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
-def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
-def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
-def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
-def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ReleaseAtCycles = [12]; }
-def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
-def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
-def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
-def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
-def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ReleaseAtCycles = [14]; }
+def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ResourceCycles = [ 5]; }
+def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ResourceCycles = [ 7]; }
+def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 5]; }
+def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 9]; }
+def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [10]; }
+def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ResourceCycles = [ 9]; }
+def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ResourceCycles = [ 9]; }
+def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ResourceCycles = [12]; }
+def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [12]; }
+def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [13]; }
+def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ResourceCycles = [14]; }
+def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ResourceCycles = [15]; }
+def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ResourceCycles = [14]; }
// Miscellaneous
// -----------------------------------------------------------------------------
diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
index af4a0176e44ee4..542d9afb59753d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -66,9 +66,9 @@ def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
// Integer Mul/MAC/Div
def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
+ let ResourceCycles = [12]; }
def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
@@ -94,7 +94,7 @@ def : WriteRes<WriteFImm, [TSV110UnitF]> { let Latency = 2; }
def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
// FP Div, Sqrt
-def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
+def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
def : WriteRes<WriteVd, [TSV110UnitF]> { let Latency = 4; }
def : WriteRes<WriteVq, [TSV110UnitF]> { let Latency = 4; }
@@ -146,7 +146,7 @@ def TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; }
def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
def TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }
-def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles = [2]; }
+def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ResourceCycles = [2]; }
def TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; }
def TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; }
def TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; }
@@ -172,25 +172,25 @@ def TSV110Wr_7cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 7; }
def TSV110Wr_8cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 8; }
-def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles = [11]; }
+def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ResourceCycles = [11]; }
-def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles = [12]; }
+def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ResourceCycles = [12]; }
-def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles = [17]; }
+def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ResourceCycles = [17]; }
-def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
+def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
-def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles = [20]; }
+def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ResourceCycles = [20]; }
-def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles = [24]; }
+def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ResourceCycles = [24]; }
-def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ReleaseAtCycles = [31]; }
+def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ResourceCycles = [31]; }
-def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ReleaseAtCycles = [36]; }
+def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ResourceCycles = [36]; }
-def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ReleaseAtCycles = [38]; }
+def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ResourceCycles = [38]; }
-def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ReleaseAtCycles = [64]; }
+def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ResourceCycles = [64]; }
//===----------------------------------------------------------------------===//
// Define Generic 2 micro-op types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index e1536f208e448a..8b380ae0e8f3cc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -59,23 +59,23 @@ def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
// MAC
def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
let Latency = 4;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
let Latency = 4;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
// Div
def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
let Latency = 12;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
}
def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
let Latency = 14;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
// Load
@@ -86,32 +86,32 @@ def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
// Vector Load
def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
let Latency = 8;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 6;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 12;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
// Pre/Post Indexing
@@ -129,12 +129,12 @@ def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;
def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 10;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
}
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@@ -162,29 +162,29 @@ def : WriteRes<WriteVq, [THXT8XUnitFPALU]> { let Latency = 6; }
def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
let Latency = 22;
- let ReleaseAtCycles = [19];
+ let ResourceCycles = [19];
}
def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }
def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 12;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 22;
- let ReleaseAtCycles = [19];
+ let ResourceCycles = [19];
}
def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 17;
- let ReleaseAtCycles = [14];
+ let ResourceCycles = [14];
}
def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 31;
- let ReleaseAtCycles = [28];
+ let ResourceCycles = [28];
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index 89faa92155e00d..cdafa33da05480 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -113,14 +113,14 @@ def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
// 23 cycles on I1.
def THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 23;
- let ReleaseAtCycles = [13, 23];
+ let ResourceCycles = [13, 23];
let NumMicroOps = 4;
}
// 39 cycles on I1.
def THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 39;
- let ReleaseAtCycles = [13, 39];
+ let ResourceCycles = [13, 39];
let NumMicroOps = 4;
}
@@ -200,14 +200,14 @@ def THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let NumMicroOps = 3;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
// 23 cycles on F0 or F1.
def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let NumMicroOps = 3;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
// 1 cycles on LS0 or LS1.
@@ -418,7 +418,7 @@ def : InstRW<[THX2T99Write_1Cyc_I2],
// Address generation
def : WriteRes<WriteI, [THX2T99I012]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -440,7 +440,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX2T99I012]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
@@ -459,7 +459,7 @@ def : InstRW<[WriteISReg],
def : WriteRes<WriteIEReg, [THX2T99I012]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -502,14 +502,14 @@ def : WriteRes<WriteIS, [THX2T99I012]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX2T99I1]> {
let Latency = 39;
- let ReleaseAtCycles = [39];
+ let ResourceCycles = [39];
let NumMicroOps = 4;
}
// Divide, X-form
def : WriteRes<WriteID64, [THX2T99I1]> {
let Latency = 23;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
let NumMicroOps = 4;
}
@@ -1110,36 +1110,36 @@ def : WriteRes<WriteFCmp, [THX2T99F01]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX2T99F01]> {
let Latency = 22;
- let ReleaseAtCycles = [19];
+ let ResourceCycles = [19];
}
def THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 4;
}
def THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 4;
}
@@ -1163,19 +1163,19 @@ def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX2T99F01]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
@@ -1254,12 +1254,12 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : WriteRes<WriteVq, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
// ASIMD arith, reduce, 4H/4S
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 8685554b00d76d..b7d337dfa76dc0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -143,14 +143,14 @@ def THX3T110Write_7Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
// 23 cycles on I1.
def THX3T110Write_23Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 23;
- let ReleaseAtCycles = [13, 23];
+ let ResourceCycles = [13, 23];
let NumMicroOps = 4;
}
// 39 cycles on I1.
def THX3T110Write_39Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 39;
- let ReleaseAtCycles = [13, 39];
+ let ResourceCycles = [13, 39];
let NumMicroOps = 4;
}
@@ -278,14 +278,14 @@ def THX3T110Write_10Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
def THX3T110Write_16Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let NumMicroOps = 3;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
// 23 cycles on F0/F1/F2/F3.
def THX3T110Write_23Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let NumMicroOps = 3;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
// 1 cycle on LS0/LS1.
@@ -304,7 +304,7 @@ def THX3T110Write_2Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// 5 cycles on LS0/LS1.
@@ -326,7 +326,7 @@ def THX3T110Write_6Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [4, 5];
+ let ResourceCycles = [4, 5];
}
// 4 + 8 cycles on LS0/LS1.
@@ -336,7 +336,7 @@ def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_8Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [4, 8];
+ let ResourceCycles = [4, 8];
}
// 11 cycles on LS0/LS1 and I1.
@@ -607,7 +607,7 @@ def THX3T110Write_3_4Cyc_F23_F0123 :
SchedWriteRes<[THX3T110FP23, THX3T110FP0123]> {
let Latency = 3;
let NumMicroOps = 2;
- let ReleaseAtCycles = [3, 4];
+ let ResourceCycles = [3, 4];
}
@@ -678,7 +678,7 @@ def : InstRW<[THX3T110Write_1Cyc_I23],
// Address generation
def : WriteRes<WriteI, [THX3T110I0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -700,7 +700,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX3T110I0123]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
@@ -719,7 +719,7 @@ def : InstRW<[WriteISReg],
def : WriteRes<WriteIEReg, [THX3T110I0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -762,14 +762,14 @@ def : WriteRes<WriteIS, [THX3T110I0123]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX3T110I1]> {
let Latency = 39;
- let ReleaseAtCycles = [39];
+ let ResourceCycles = [39];
let NumMicroOps = 4;
}
// Divide, X-form
def : WriteRes<WriteID64, [THX3T110I1]> {
let Latency = 23;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
let NumMicroOps = 4;
}
@@ -1218,36 +1218,36 @@ def : WriteRes<WriteFCmp, [THX3T110FP0123]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX3T110FP0123]> {
let Latency = 22;
- let ReleaseAtCycles = [19];
+ let ResourceCycles = [19];
}
def THX3T110XWriteFDiv : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFDivSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFDivDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 4;
}
def THX3T110XWriteFSqrtSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFSqrtDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 4;
}
@@ -1271,19 +1271,19 @@ def : InstRW<[THX3T110Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX3T110FP0123]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX3T110XWriteFMul : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX3T110XWriteFMulAcc : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 3;
}
@@ -1362,12 +1362,12 @@ def : InstRW<[THX3T110Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : WriteRes<WriteVq, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
// ASIMD arith, reduce, 4H/4S
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 3af71727c5b741..2d53b2a70dbe05 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -271,7 +271,7 @@ GCNHazardRecognizer::getMFMAPipelineWaitStates(const MachineInstr &MI) const {
const MCSchedClassDesc *SC = TSchedModel.resolveSchedClass(&MI);
assert(TSchedModel.getWriteProcResBegin(SC) !=
TSchedModel.getWriteProcResEnd(SC));
- return TSchedModel.getWriteProcResBegin(SC)->ReleaseAtCycle;
+ return TSchedModel.getWriteProcResBegin(SC)->Cycles;
}
void GCNHazardRecognizer::processBundle() {
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index 3d1631fc046195..382e5c3b8480a5 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -157,13 +157,13 @@ multiclass SICommonWriteRes {
def : HWVALUWriteRes<Write4PassDGEMM, 4>;
def : HWVALUWriteRes<Write8PassDGEMM, 16>;
- let ReleaseAtCycles = [2] in
+ let ResourceCycles = [2] in
def : HWWriteRes<Write2PassMAI, [HWXDL], 2>;
- let ReleaseAtCycles = [4] in
+ let ResourceCycles = [4] in
def : HWWriteRes<Write4PassMAI, [HWXDL], 4>;
- let ReleaseAtCycles = [8] in
+ let ResourceCycles = [8] in
def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;
- let ReleaseAtCycles = [16] in
+ let ResourceCycles = [16] in
def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
} // End RetireOOO = 1
diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index b28de7873b3059..53a2a6fec51e99 100644
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -49,7 +49,7 @@
// NumMicroOps = 2; // Dispatch 2 micro-ops.
// // The two instances of resource P01 are occupied for one cycle. It is one
// // cycle because these resources happen to be pipelined.
-// ReleaseAtCycles = [1, 1];
+// ResourceCycles = [1, 1];
// }
// def : ReadAdvance<ReadAdvanceALUsr, 3>;
@@ -195,7 +195,7 @@ class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
list<int> rcl, SchedWriteRes wr> :
SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
let Latency = !add(wr.Latency, lat);
- let ReleaseAtCycles = !listconcat(wr.ReleaseAtCycles, rcl);
+ let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
let NumMicroOps = !add(wr.NumMicroOps, uops);
SchedWriteRes BaseWr = wr;
}
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td b/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
index 025023c5f41a9e..531b10bc5cfd4a 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
@@ -28,30 +28,30 @@ def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
- let ReleaseAtCycles = [17]; }
+ let ResourceCycles = [17]; }
def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
- let ReleaseAtCycles = [18]; }
+ let ResourceCycles = [18]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
- let ReleaseAtCycles = [19]; }
+ let ResourceCycles = [19]; }
def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1;
- let ReleaseAtCycles = [1]; }
+ let ResourceCycles = [1]; }
def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2;
- let ReleaseAtCycles = [1]; }
+ let ResourceCycles = [1]; }
def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2;
- let ReleaseAtCycles = [1]; }
+ let ResourceCycles = [1]; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
- let ReleaseAtCycles = [32]; }
+ let ResourceCycles = [32]; }
def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
- let ReleaseAtCycles = [32]; }
+ let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
- let ReleaseAtCycles = [35]; }
+ let ResourceCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
@@ -89,7 +89,7 @@ def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 64;
let NumMicroOps = 2;
- let ReleaseAtCycles = [32, 32];
+ let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
@@ -224,7 +224,7 @@ def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 36;
let NumMicroOps = 2;
- let ReleaseAtCycles = [18, 18];
+ let ResourceCycles = [18, 18];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td
index a0f56a69b2bb14..8b375d3602c240 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA9.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA9.td
@@ -1995,15 +1995,15 @@ def : WriteRes<WriteVST4, []>;
// Reserve A9UnitFP for 2 consecutive cycles.
def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 4;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 7;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 9;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
// Branches don't have a def operand but still consume resources.
diff --git a/llvm/lib/Target/ARM/ARMScheduleM55.td b/llvm/lib/Target/ARM/ARMScheduleM55.td
index 35724703b4c322..f24f97b26f0aa5 100644
--- a/llvm/lib/Target/ARM/ARMScheduleM55.td
+++ b/llvm/lib/Target/ARM/ARMScheduleM55.td
@@ -46,7 +46,7 @@
//
// For this schedule, we currently model latencies and pipelines well for each
// instruction. MVE instruction take two beats, modelled using
-// ReleaseAtCycles=[2].
+// ResourceCycles=[2].
//
//
// Dual Issue
@@ -245,7 +245,7 @@ def : ReadAdvance<ReadMAC, 0>;
// MVE and VFP //
//=============//
-// The Writes that take ReleaseAtCycles=[2] are MVE instruction, the others VFP.
+// The Writes that take ResourceCycles=[2] are MVE instruction, the others VFP.
let SingleIssue = 1, Latency = 1 in {
def M55WriteLSE2 : SchedWriteRes<[M55UnitLoadStore]>;
@@ -253,10 +253,10 @@ let SingleIssue = 1, Latency = 1 in {
def M55WriteFloatE2 : SchedWriteRes<[M55UnitVecFPALU]>;
def M55WriteSysE2 : SchedWriteRes<[M55UnitVecSys]>;
- def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
- def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
- def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
- def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ReleaseAtCycles=[2]; }
+ def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
+ def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
+ def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
+ def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 2 in {
@@ -264,20 +264,20 @@ let SingleIssue = 1, Latency = 2 in {
def M55WriteIntE3 : SchedWriteRes<[M55UnitVecALU]>;
def M55WriteFloatE3 : SchedWriteRes<[M55UnitVecFPALU]>;
- def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
- def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
- def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
+ def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
+ def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
+ def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 3 in {
- def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
+ def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
// Same as M55Write2IntE3/M55Write2FloatE3 above, but longer latency and no forwarding into stores
- def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
- def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
+ def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
+ def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 4 in {
- def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
+ def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55WriteFloatE3Plus2 : SchedWriteRes<[M55UnitVecFPALU]>;
}
let SingleIssue = 1, Latency = 9 in {
diff --git a/llvm/lib/Target/ARM/ARMScheduleM85.td b/llvm/lib/Target/ARM/ARMScheduleM85.td
index cd375a16305ec8..0202e4ad4e5f9b 100644
--- a/llvm/lib/Target/ARM/ARMScheduleM85.td
+++ b/llvm/lib/Target/ARM/ARMScheduleM85.td
@@ -327,7 +327,7 @@ def M85StoreDP : SchedWriteRes<[M85UnitStoreL, M85UnitStoreH,
M85UnitVPortL, M85UnitVPortH]>;
def M85StoreSys : SchedWriteRes<[M85UnitStore, M85UnitVPort,
M85UnitVFPA, M85UnitVFPB, M85UnitVFPC, M85UnitVFPD]>;
-let ReleaseAtCycles = [2,2,1,1], EndGroup = 1 in {
+let ResourceCycles = [2,2,1,1], EndGroup = 1 in {
def M85LoadMVE : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
M85UnitVPortL, M85UnitVPortH]>;
def M85LoadMVELate : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
@@ -702,49 +702,49 @@ def : InstRW<[M85OverrideVFPLat4, WriteFPMAC64,
let Latency = 4, EndGroup = 1 in {
def M85GrpALat2MveR : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpABLat2MveR : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat2MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85Lat2MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
def M85GrpBLat4Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
}
let Latency = 3, EndGroup = 1 in {
def M85GrpBLat3Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpBLat1MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85Lat1MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
}
let Latency = 2, EndGroup = 1 in {
def M85GrpALat2Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpABLat2Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat2Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85Lat2Mve : SchedWriteRes<[]> { let NumMicroOps = 0; }
}
let Latency = 1, EndGroup = 1 in {
def M85GrpALat1Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpABLat1Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat1Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpCLat1Mve : SchedWriteRes<[M85UnitVFPCL, M85UnitVFPCH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,2,1,1,1];
+ let ResourceCycles = [2,2,1,1,1];
}
def M85GrpDLat1Mve : SchedWriteRes<[M85UnitVFPD, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
- let ReleaseAtCycles = [2,1,1,1];
+ let ResourceCycles = [2,1,1,1];
}
}
diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td
index e85646915117c7..466acec6f76ae3 100644
--- a/llvm/lib/Target/ARM/ARMScheduleR52.td
+++ b/llvm/lib/Target/ARM/ARMScheduleR52.td
@@ -72,7 +72,7 @@ def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }
// Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2)
def : WriteRes<WriteDIV, [R52UnitDiv]> {
- let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
+ let Latency = 8; let ResourceCycles = [8]; // non-pipelined
}
// Branches - LR written in Late EX2
@@ -107,12 +107,12 @@ def : WriteRes<WriteFPMAC64, [R52UnitFPMUL, R52UnitFPMUL,
def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
let Latency = 7; // FP div takes fixed #cycles
- let ReleaseAtCycles = [7]; // is not pipelined
+ let ResourceCycles = [7]; // is not pipelined
}
def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
let Latency = 17;
- let ReleaseAtCycles = [17];
+ let ResourceCycles = [17];
}
def : WriteRes<WriteFPSQRT32, [R52UnitDiv]> { let Latency = 7; }
@@ -145,7 +145,7 @@ def R52WriteMACHi : SchedWriteRes<[R52UnitMAC]> {
let Latency = 4; let NumMicroOps = 0;
}
def R52WriteDIV : SchedWriteRes<[R52UnitDiv]> {
- let Latency = 8; let ReleaseAtCycles = [8]; // not pipelined
+ let Latency = 8; let ResourceCycles = [8]; // not pipelined
}
def R52WriteLd : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
def R52WriteST : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
@@ -552,7 +552,7 @@ foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> {
let Latency = 0;
let NumMicroOps = Num;
- let ReleaseAtCycles = [Num];
+ let ResourceCycles = [Num];
}
}
def R52WriteVLDM : SchedWriteVariant<[
@@ -639,57 +639,57 @@ def R52WriteVLDM : SchedWriteVariant<[
def R52WriteSTM5 : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def R52WriteSTM6 : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def R52WriteSTM7 : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 6;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def R52WriteSTM8 : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def R52WriteSTM9 : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 10;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
}
def R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> {
let Latency = 10;
let NumMicroOps = 12;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
}
def R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> {
let Latency = 11;
let NumMicroOps = 14;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> {
let Latency = 12;
let NumMicroOps = 16;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> {
let Latency = 13;
let NumMicroOps = 18;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> {
let Latency = 14;
let NumMicroOps = 20;
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
}
def R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> {
let Latency = 15;
let NumMicroOps = 22;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def R52WriteSTM : SchedWriteVariant<[
@@ -719,45 +719,45 @@ def : WriteRes<WriteVLD1, [R52UnitLd]> { let Latency = 5;}
def : WriteRes<WriteVLD2, [R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD3, [R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD4, [R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let SingleIssue = 1;
}
def R52WriteVST1Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def R52WriteVST2Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def R52WriteVST3Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def R52WriteVST4Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def R52WriteVST5Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 9;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
}
diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td
index 88682f5c0d2c42..d66b3065c7b746 100644
--- a/llvm/lib/Target/ARM/ARMScheduleSwift.td
+++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td
@@ -88,7 +88,7 @@ let SchedModel = SwiftModel in {
def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
// Plain load without writeback.
def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
@@ -261,7 +261,7 @@ let SchedModel = SwiftModel in {
def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
def SwiftWrite1Cycle : SchedWriteRes<[]> {
let Latency = 1;
@@ -283,7 +283,7 @@ let SchedModel = SwiftModel in {
def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2, 3];
+ let ResourceCycles = [2, 3];
}
// Aliasing sub-target specific WriteRes to generic ones
@@ -313,7 +313,7 @@ let SchedModel = SwiftModel in {
def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 14;
- let ReleaseAtCycles = [1, 14];
+ let ResourceCycles = [1, 14];
}
// 4.2.18 Integer Divide
def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
@@ -653,15 +653,15 @@ let SchedModel = SwiftModel in {
// Serializing instructions.
def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 15;
- let ReleaseAtCycles = [15];
+ let ResourceCycles = [15];
}
def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 15;
- let ReleaseAtCycles = [15];
+ let ResourceCycles = [15];
}
def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 15;
- let ReleaseAtCycles = [15];
+ let ResourceCycles = [15];
}
def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
(instregex "VMRS")>;
@@ -684,7 +684,7 @@ let SchedModel = SwiftModel in {
def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 0;
let NumMicroOps = Num;
- let ReleaseAtCycles = [Num];
+ let ResourceCycles = [Num];
}
}
@@ -860,17 +860,17 @@ let SchedModel = SwiftModel in {
// 4.2.43 Advanced SIMD, Element or Structure Load and Store
def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
foreach Num = 1-2 in {
def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 0;
let NumMicroOps = Num;
- let ReleaseAtCycles = [Num];
+ let ResourceCycles = [Num];
}
}
// VLDx
@@ -1038,12 +1038,12 @@ let SchedModel = SwiftModel in {
def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 17;
- let ReleaseAtCycles = [1, 15];
+ let ResourceCycles = [1, 15];
}
def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 32;
- let ReleaseAtCycles = [1, 30];
+ let ResourceCycles = [1, 30];
}
def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
@@ -1086,7 +1086,7 @@ let SchedModel = SwiftModel in {
def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
// Preload.
def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
- let ReleaseAtCycles = [0];
+ let ResourceCycles = [0];
}
}
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index a3df88a93cfb1f..931412cb261ef4 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -160,12 +160,12 @@ def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> {
def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 33;
- let ReleaseAtCycles = [33];
+ let ResourceCycles = [33];
}
def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 31;
- let ReleaseAtCycles = [31];
+ let ResourceCycles = [31];
}
// mul
@@ -761,35 +761,35 @@ def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> {
}
def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
- let ReleaseAtCycles = [ 14 ];
+ let ResourceCycles = [ 14 ];
}
def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
- let ReleaseAtCycles = [ 29 ];
+ let ResourceCycles = [ 29 ];
}
def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 13;
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
}
def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 25;
- let ReleaseAtCycles = [ 21 ];
+ let ResourceCycles = [ 21 ];
}
def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
- let ReleaseAtCycles = [ 14 ];
+ let ResourceCycles = [ 14 ];
}
def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
- let ReleaseAtCycles = [ 29 ];
+ let ResourceCycles = [ 29 ];
}
def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
- let ReleaseAtCycles = [ 14 ];
+ let ResourceCycles = [ 14 ];
}
def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 29;
- let ReleaseAtCycles = [ 29 ];
+ let ResourceCycles = [ 29 ];
}
// Floating point compare and branch
@@ -1405,7 +1405,7 @@ let Latency = 5;
}
def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> {
let Latency = 33;
- let ReleaseAtCycles = [ 33 ];
+ let ResourceCycles = [ 33 ];
}
// FPUS is also used in moves from floating point and MSA registers to general
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index c79cd876596c04..466b5c6af69637 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -119,7 +119,7 @@ def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>;
def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
// FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
// not during 0, 1, and 2.
- let ReleaseAtCycles = [ 1, 3 ];
+ let ResourceCycles = [ 1, 3 ];
}
def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
@@ -165,12 +165,12 @@ def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
- let ReleaseAtCycles = [1, 34];
+ let ResourceCycles = [1, 34];
}
def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
- let ReleaseAtCycles = [1, 34];
+ let ResourceCycles = [1, 34];
}
def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
@@ -241,47 +241,47 @@ def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6;
def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
- let ReleaseAtCycles = [ 1, 23 ];
+ let ResourceCycles = [ 1, 23 ];
}
def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
- let ReleaseAtCycles = [ 1, 23 ];
+ let ResourceCycles = [ 1, 23 ];
}
def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 31 / 35
let Latency = 31; // Using common case
- let ReleaseAtCycles = [ 1, 31 ];
+ let ResourceCycles = [ 1, 31 ];
}
def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 19 / 23
let Latency = 19; // Using common case
- let ReleaseAtCycles = [ 1, 19 ];
+ let ResourceCycles = [ 1, 19 ];
}
def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
- let ReleaseAtCycles = [ 1, 27 ];
+ let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 27
let Latency = 27; // Using common case
- let ReleaseAtCycles = [ 1, 27 ];
+ let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
- let ReleaseAtCycles = [ 1, 27 ];
+ let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
- let ReleaseAtCycles = [ 1, 27 ];
+ let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 35 / 39
let Latency = 35; // Using common case
- let ReleaseAtCycles = [ 1, 35 ];
+ let ResourceCycles = [ 1, 35 ];
}
def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP10.td b/llvm/lib/Target/PowerPC/PPCScheduleP10.td
index 9bbb605d4be0f6..25be37718af241 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP10.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP10.td
@@ -87,27 +87,27 @@ let SchedModel = P10Model in {
}
def P10W_BF_22C : SchedWriteRes<[P10_BF]> {
- let ReleaseAtCycles = [ 5 ];
+ let ResourceCycles = [ 5 ];
let Latency = 22;
}
def P10W_BF_24C : SchedWriteRes<[P10_BF]> {
- let ReleaseAtCycles = [ 8 ];
+ let ResourceCycles = [ 8 ];
let Latency = 24;
}
def P10W_BF_26C : SchedWriteRes<[P10_BF]> {
- let ReleaseAtCycles = [ 5 ];
+ let ResourceCycles = [ 5 ];
let Latency = 26;
}
def P10W_BF_27C : SchedWriteRes<[P10_BF]> {
- let ReleaseAtCycles = [ 7 ];
+ let ResourceCycles = [ 7 ];
let Latency = 27;
}
def P10W_BF_36C : SchedWriteRes<[P10_BF]> {
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
let Latency = 36;
}
@@ -128,134 +128,134 @@ let SchedModel = P10Model in {
}
def P10W_DF_24C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 16 ];
+ let ResourceCycles = [ 16 ];
let Latency = 24;
}
def P10W_DF_25C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 17 ];
+ let ResourceCycles = [ 17 ];
let Latency = 25;
}
def P10W_DF_26C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 18 ];
+ let ResourceCycles = [ 18 ];
let Latency = 26;
}
def P10W_DF_32C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 22 ];
+ let ResourceCycles = [ 22 ];
let Latency = 32;
}
def P10W_DF_33C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 25 ];
+ let ResourceCycles = [ 25 ];
let Latency = 33;
}
def P10W_DF_34C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 25 ];
+ let ResourceCycles = [ 25 ];
let Latency = 34;
}
def P10W_DF_38C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 30 ];
+ let ResourceCycles = [ 30 ];
let Latency = 38;
}
def P10W_DF_40C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 17 ];
+ let ResourceCycles = [ 17 ];
let Latency = 40;
}
def P10W_DF_43C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 34 ];
+ let ResourceCycles = [ 34 ];
let Latency = 43;
}
def P10W_DF_59C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 49 ];
+ let ResourceCycles = [ 49 ];
let Latency = 59;
}
def P10W_DF_61C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 12 ];
+ let ResourceCycles = [ 12 ];
let Latency = 61;
}
def P10W_DF_68C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 15 ];
+ let ResourceCycles = [ 15 ];
let Latency = 68;
}
def P10W_DF_77C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 67 ];
+ let ResourceCycles = [ 67 ];
let Latency = 77;
}
def P10W_DF_87C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 12 ];
+ let ResourceCycles = [ 12 ];
let Latency = 87;
}
def P10W_DF_100C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 32 ];
+ let ResourceCycles = [ 32 ];
let Latency = 100;
}
def P10W_DF_174C : SchedWriteRes<[P10_DF]> {
- let ReleaseAtCycles = [ 33 ];
+ let ResourceCycles = [ 33 ];
let Latency = 174;
}
// A DV pipeline may take from 20 to 83 cycles to complete.
// Some DV operations may keep the pipeline busy for up to 33 cycles.
def P10W_DV_20C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
let Latency = 20;
}
def P10W_DV_25C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
let Latency = 25;
}
def P10W_DV_27C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
let Latency = 27;
}
def P10W_DV_41C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 10 ];
+ let ResourceCycles = [ 10 ];
let Latency = 41;
}
def P10W_DV_43C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 21 ];
+ let ResourceCycles = [ 21 ];
let Latency = 43;
}
def P10W_DV_47C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 21 ];
+ let ResourceCycles = [ 21 ];
let Latency = 47;
}
def P10W_DV_54C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 33 ];
+ let ResourceCycles = [ 33 ];
let Latency = 54;
}
def P10W_DV_60C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 33 ];
+ let ResourceCycles = [ 33 ];
let Latency = 60;
}
def P10W_DV_75C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 21 ];
+ let ResourceCycles = [ 21 ];
let Latency = 75;
}
def P10W_DV_83C : SchedWriteRes<[P10_DV]> {
- let ReleaseAtCycles = [ 33 ];
+ let ResourceCycles = [ 33 ];
let Latency = 83;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
index 36befceef4ac18..b763191d980e46 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -227,17 +227,17 @@ let SchedModel = P9Model in {
}
def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 16;
}
def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 24;
}
def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 40;
}
@@ -261,62 +261,62 @@ let SchedModel = P9Model in {
}
def P9_DP_22C_5 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
let Latency = 22;
}
def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 24;
}
def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 24;
}
def P9_DP_26C_5 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
let Latency = 22;
}
def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let Latency = 27;
}
def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let Latency = 27;
}
def P9_DP_33C_8 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 33;
}
def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 33;
}
def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let Latency = 33;
}
def P9_DP_36C_10 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let Latency = 36;
}
def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let Latency = 36;
}
def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let Latency = 36;
}
@@ -358,27 +358,27 @@ let SchedModel = P9Model in {
def P9_DFU_23C : SchedWriteRes<[DFU]> {
let Latency = 23;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def P9_DFU_24C : SchedWriteRes<[DFU]> {
let Latency = 24;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
}
def P9_DFU_37C : SchedWriteRes<[DFU]> {
let Latency = 37;
- let ReleaseAtCycles = [25];
+ let ResourceCycles = [25];
}
def P9_DFU_58C : SchedWriteRes<[DFU]> {
let Latency = 58;
- let ReleaseAtCycles = [44];
+ let ResourceCycles = [44];
}
def P9_DFU_76C : SchedWriteRes<[DFU]> {
let Latency = 76;
- let ReleaseAtCycles = [62];
+ let ResourceCycles = [62];
}
// 2 or 5 cycle latencies for the branch unit.
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 8fbc9afe267c56..b14cdd40f154ae 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -70,11 +70,11 @@ def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
// Worst case latency is used.
def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
let Latency = 34;
- let ReleaseAtCycles = [34];
+ let ResourceCycles = [34];
}
def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
let Latency = 33;
- let ReleaseAtCycles = [33];
+ let ResourceCycles = [33];
}
// Memory
@@ -157,16 +157,16 @@ def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
// FP division
// FP division unit on Rocket is not pipelined, so set resource cycles to latency.
-let Latency = 20, ReleaseAtCycles = [20] in {
+let Latency = 20, ResourceCycles = [20] in {
def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
}
// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
+ let ResourceCycles = [20]; }
def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
- let ReleaseAtCycles = [25]; }
+ let ResourceCycles = [25]; }
// Others
def : WriteRes<WriteCSR, []>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index f1049f2b3ee741..0c1df8458e7aa8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -256,11 +256,11 @@ def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
// Integer division
def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 66;
- let ReleaseAtCycles = [1, 65];
+ let ResourceCycles = [1, 65];
}
def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 34;
- let ReleaseAtCycles = [1, 33];
+ let ResourceCycles = [1, 33];
}
// Bitmanip
@@ -346,7 +346,7 @@ def : WriteRes<WriteFSGNJ16, [SiFive7PipeB]>;
def : WriteRes<WriteFMinMax16, [SiFive7PipeB]>;
}
-let Latency = 14, ReleaseAtCycles = [1, 13] in {
+let Latency = 14, ResourceCycles = [1, 13] in {
def : WriteRes<WriteFDiv16, [SiFive7PipeB, SiFive7FDiv]>;
def : WriteRes<WriteFSqrt16, [SiFive7PipeB, SiFive7FDiv]>;
}
@@ -363,9 +363,9 @@ def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
}
def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
- let ReleaseAtCycles = [1, 26]; }
+ let ResourceCycles = [1, 26]; }
def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
- let ReleaseAtCycles = [1, 26]; }
+ let ResourceCycles = [1, 26]; }
// Double precision
let Latency = 7 in {
@@ -379,9 +379,9 @@ def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
}
def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
- let ReleaseAtCycles = [1, 55]; }
+ let ResourceCycles = [1, 55]; }
def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
- let ReleaseAtCycles = [1, 55]; }
+ let ResourceCycles = [1, 55]; }
// Conversions
let Latency = 3 in {
@@ -431,20 +431,20 @@ def : WriteRes<WriteVSETVL, [SiFive7PipeA]>;
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDE", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDFF", [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in
+ let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSTE", [SiFive7VS], mx, IsWorstCase>;
}
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetMaskLoadStoreCycles<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in
+ let Latency = 4, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVLDM", [SiFive7VL], mx, IsWorstCase>;
- let Latency = 1, ReleaseAtCycles = [Cycles] in
+ let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSTM", [SiFive7VS], mx, IsWorstCase>;
}
@@ -458,12 +458,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS8", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS8", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VS], mx, IsWorstCase>;
@@ -472,12 +472,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS16", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS16", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VS], mx, IsWorstCase>;
@@ -486,12 +486,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS32", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS32", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VS], mx, IsWorstCase>;
@@ -500,12 +500,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS64", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS64", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VS], mx, IsWorstCase>;
@@ -513,22 +513,22 @@ foreach mx = SchedMxList in {
}
// VLD*R is LMUL aware
-let Latency = 4, ReleaseAtCycles = [2] in
+let Latency = 4, ResourceCycles = [2] in
def : WriteRes<WriteVLD1R, [SiFive7VL]>;
-let Latency = 4, ReleaseAtCycles = [4] in
+let Latency = 4, ResourceCycles = [4] in
def : WriteRes<WriteVLD2R, [SiFive7VL]>;
-let Latency = 4, ReleaseAtCycles = [8] in
+let Latency = 4, ResourceCycles = [8] in
def : WriteRes<WriteVLD4R, [SiFive7VL]>;
-let Latency = 4, ReleaseAtCycles = [16] in
+let Latency = 4, ResourceCycles = [16] in
def : WriteRes<WriteVLD8R, [SiFive7VL]>;
// VST*R is LMUL aware
-let Latency = 1, ReleaseAtCycles = [2] in
+let Latency = 1, ResourceCycles = [2] in
def : WriteRes<WriteVST1R, [SiFive7VS]>;
-let Latency = 1, ReleaseAtCycles = [4] in
+let Latency = 1, ResourceCycles = [4] in
def : WriteRes<WriteVST2R, [SiFive7VS]>;
-let Latency = 1, ReleaseAtCycles = [8] in
+let Latency = 1, ResourceCycles = [8] in
def : WriteRes<WriteVST4R, [SiFive7VS]>;
-let Latency = 1, ReleaseAtCycles = [16] in
+let Latency = 1, ResourceCycles = [16] in
def : WriteRes<WriteVST8R, [SiFive7VS]>;
// Segmented Loads and Stores
@@ -542,21 +542,21 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesSegmentedSeg2<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in
+ let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew, [SiFive7VS], mx, IsWorstCase>;
foreach nf=3-8 in {
defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in
+ let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
}
}
@@ -567,12 +567,12 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
- let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
- let Latency = 1, ReleaseAtCycles = [Cycles] in {
+ let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
@@ -585,7 +585,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VA], mx, IsWorstCase>;
@@ -609,7 +609,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VA], mx, IsWorstCase>;
}
// Mask results can't chain.
- let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VA], mx, IsWorstCase>;
@@ -618,7 +618,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVExtV", [SiFive7VA], mx, IsWorstCase>;
}
}
@@ -627,7 +627,7 @@ foreach mx = SchedMxList in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ let Latency = Cycles, ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VA], mx, sew, IsWorstCase>;
}
@@ -638,7 +638,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFive7VA], mx, IsWorstCase>;
@@ -652,7 +652,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFive7VA], mx, IsWorstCase>;
@@ -663,7 +663,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUI", [SiFive7VA], mx, IsWorstCase>;
@@ -680,7 +680,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVNClipV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipI", [SiFive7VA], mx, IsWorstCase>;
@@ -691,7 +691,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VA], mx, IsWorstCase>;
@@ -702,7 +702,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
}
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMinMaxV", [SiFive7VA], mx, IsWorstCase>;
@@ -712,7 +712,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>;
}
// Mask results can't chain.
- let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>;
}
@@ -722,7 +722,7 @@ foreach mx = SchedMxListF in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ let Latency = Cycles, ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFive7VA], mx, sew, IsWorstCase>;
@@ -734,14 +734,14 @@ foreach mx = SchedMxListF in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
}
}
foreach mx = SchedMxListFW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFWALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFWMulV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFWMulAddV", [SiFive7VA], mx, IsWorstCase>;
@@ -756,14 +756,14 @@ foreach mx = SchedMxListFW in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
}
}
foreach mx = SchedMxListFW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VA], mx, IsWorstCase>;
}
@@ -774,7 +774,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in
+ let Latency = Cycles, ResourceCycles = [Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
@@ -786,7 +786,7 @@ foreach mx = SchedMxListWRed in {
foreach sew = SchedSEWSet<mx, 0, 1>.val in {
defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in
+ let Latency = Cycles, ResourceCycles = [Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@@ -796,14 +796,14 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, 1>.val in {
defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in {
+ let Latency = RedCycles, ResourceCycles = [RedCycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
- let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
+ let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@@ -813,11 +813,11 @@ foreach mx = SchedMxListFWRed in {
foreach sew = SchedSEWSet<mx, 1, 1>.val in {
defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
- let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in
+ let Latency = RedCycles, ResourceCycles = [RedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
- let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
+ let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@@ -827,7 +827,7 @@ foreach mx = SchedMxListFWRed in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VA], mx, IsWorstCase>;
@@ -837,14 +837,14 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>;
}
}
// 16. Vector Permutation Instructions
-let Latency = 4, ReleaseAtCycles = [1] in {
+let Latency = 4, ResourceCycles = [1] in {
def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
@@ -853,7 +853,7 @@ let Latency = 4, ReleaseAtCycles = [1] in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [Cycles] in {
+ let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>;
}
@@ -863,7 +863,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
+ let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VA], mx, sew, IsWorstCase>;
}
@@ -873,7 +873,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 4, ReleaseAtCycles = [Cycles] in {
+ let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VA], mx, IsWorstCase>;
@@ -882,13 +882,13 @@ foreach mx = SchedMxList in {
}
// VMov*V is LMUL Aware
-let Latency = 4, ReleaseAtCycles = [2] in
+let Latency = 4, ResourceCycles = [2] in
def : WriteRes<WriteVMov1V, [SiFive7VA]>;
-let Latency = 4, ReleaseAtCycles = [4] in
+let Latency = 4, ResourceCycles = [4] in
def : WriteRes<WriteVMov2V, [SiFive7VA]>;
-let Latency = 4, ReleaseAtCycles = [8] in
+let Latency = 4, ResourceCycles = [8] in
def : WriteRes<WriteVMov4V, [SiFive7VA]>;
-let Latency = 4, ReleaseAtCycles = [16] in
+let Latency = 4, ResourceCycles = [16] in
def : WriteRes<WriteVMov8V, [SiFive7VA]>;
// Others
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
index 960258c8bc7dfe..41eefa0c67d933 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -55,14 +55,14 @@ def : WriteRes<WriteIMul, [SCR1_MUL]>;
def : WriteRes<WriteIMul32, [SCR1_MUL]>;
// Integer division: latency 33, inverse throughput 33
-let Latency = 33, ReleaseAtCycles = [33] in {
+let Latency = 33, ResourceCycles = [33] in {
def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
def : WriteRes<WriteIDiv, [SCR1_DIV]>;
}
// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
// (SCR1_CFG_RV32IMC_MAX includes TCM)
-let Latency = 2, ReleaseAtCycles=[2] in {
+let Latency = 2, ResourceCycles=[2] in {
// Memory
def : WriteRes<WriteSTB, [SCR1_LSU]>;
def : WriteRes<WriteSTH, [SCR1_LSU]>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index fe84ca45374bd3..fd01a8a941c9de 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z13_VecUnit]>;
def : WriteRes<VecStr, [Z13_VecUnit]>;
def : WriteRes<VecXsPm, [Z13_VecUnit]>;
- foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
@@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
}}
- def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
+ def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z13_VBUnit]>; // Virtual Branching Unit
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index d5eab33dbb4a6e..3f406736a71ff9 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z14_VecUnit]>;
def : WriteRes<VecStr, [Z14_VecUnit]>;
def : WriteRes<VecXsPm, [Z14_VecUnit]>;
- foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
@@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
}}
- def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
+ def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z14_VBUnit]>; // Virtual Branching Unit
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 09b505fc149e00..6ae911c3f3ebe5 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z15_VecUnit]>;
def : WriteRes<VecStr, [Z15_VecUnit]>;
def : WriteRes<VecXsPm, [Z15_VecUnit]>;
- foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
@@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
}}
- def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
+ def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z15_VBUnit]>; // Virtual Branching Unit
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 695604af1b8872..ca688671a7e2e1 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z16_VecUnit]>;
def : WriteRes<VecStr, [Z16_VecUnit]>;
def : WriteRes<VecXsPm, [Z16_VecUnit]>;
- foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
@@ -104,8 +104,8 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
}}
- def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
- def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [20]; }
+ def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ResourceCycles = [30]; }
+ def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ResourceCycles = [20]; }
def : WriteRes<VBU, [Z16_VBUnit]>; // Virtual Branching Unit
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 98ea7d09490699..173cf960d2bd05 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -82,7 +82,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [Z196_LSUnit]>;
def : WriteRes<FPU, [Z196_FPUnit]>;
def : WriteRes<DFU, [Z196_DFUnit]>;
- foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-6 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index bd0bc480a00810..d2060471d65ed3 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -83,7 +83,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [ZEC12_LSUnit]>;
def : WriteRes<FPU, [ZEC12_FPUnit]>;
def : WriteRes<DFU, [ZEC12_DFUnit]>;
- foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
+ foreach Num = 2-6 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 3406a28be2c29a..eb7dcfc6108bf2 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -103,7 +103,7 @@ multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -111,7 +111,7 @@ multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([ADLPPort02_03_11], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -302,7 +302,7 @@ defm : ADLPWriteResPair<WriteFSqrt64X, [ADLPPort00], 18, [1], 1, 6>;
defm : ADLPWriteResPair<WriteFSqrt64Y, [ADLPPort00], 18, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
def : WriteRes<WriteFSqrt80, [ADLPPortInvalid, ADLPPort00]> {
- let ReleaseAtCycles = [7, 1];
+ let ResourceCycles = [7, 1];
let Latency = 21;
}
defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 7>;
@@ -517,7 +517,7 @@ def : InstRW<[ADLPWriteResGroup0], (instregex "^AA(D|N)D64mr$",
"^A(X?)OR64mr$")>;
def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 6;
}
@@ -540,7 +540,7 @@ def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, A
def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
@@ -598,7 +598,7 @@ def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_F(32|64)m$",
"^SUB(R?)_F(32|64)m$")>;
def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
@@ -645,7 +645,7 @@ def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort01_05_10]> {
def : InstRW<[ADLPWriteResGroup14], (instregex "^ANDN(32|64)rr$")>;
def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [5, 2, 1, 1];
+ let ResourceCycles = [5, 2, 1, 1];
let Latency = 10;
let NumMicroOps = 9;
}
@@ -658,7 +658,7 @@ def : InstRW<[ADLPWriteResGroup16], (instregex "^BT((C|R|S)?)64rr$",
"^P(DEP|EXT)(32|64)rr$")>;
def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 10;
}
@@ -721,14 +721,14 @@ def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09,
def : InstRW<[ADLPWriteResGroup26], (instrs CLFLUSHOPT)>;
def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup27], (instrs CLI)>;
def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
- let ReleaseAtCycles = [6, 1, 3];
+ let ResourceCycles = [6, 1, 3];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 10;
}
@@ -742,35 +742,35 @@ def : InstRW<[ADLPWriteResGroup29], (instregex "^MOV16o(16|32|64)a$")>;
def : InstRW<[ADLPWriteResGroup29], (instrs CLWB)>;
def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [5, 2];
+ let ResourceCycles = [5, 2];
let Latency = 6;
let NumMicroOps = 7;
}
def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPS(B|L|Q|W)$")>;
def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+ let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
let Latency = 32;
let NumMicroOps = 22;
}
def : InstRW<[ADLPWriteResGroup31], (instrs CMPXCHG16B)>;
def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
+ let ResourceCycles = [4, 7, 2, 1, 1, 1];
let Latency = 25;
let NumMicroOps = 16;
}
def : InstRW<[ADLPWriteResGroup32], (instrs CMPXCHG8B)>;
def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 2, 1, 1, 1];
+ let ResourceCycles = [1, 2, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
def : InstRW<[ADLPWriteResGroup33], (instrs CMPXCHG8rm)>;
def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
+ let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
let Latency = 18;
let NumMicroOps = 26;
}
@@ -791,7 +791,7 @@ def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSr
def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 8;
let NumMicroOps = 3;
}
@@ -870,7 +870,7 @@ def : InstRW<[ADLPWriteResGroup48], (instregex "^DIV_F(P?)rST0$")>;
def : InstRW<[ADLPWriteResGroup48], (instrs DIV_FST0r)>;
def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
+ let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
let Latency = 126;
let NumMicroOps = 57;
}
@@ -912,14 +912,14 @@ def : InstRW<[ADLPWriteResGroup54], (instrs FBSTPm,
VMPTRSTm)>;
def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup55], (instrs FDECSTP)>;
def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 11;
let NumMicroOps = 3;
}
@@ -937,21 +937,21 @@ def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_0
def : InstRW<[ADLPWriteResGroup58], (instrs FLDCW16m)>;
def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
- let ReleaseAtCycles = [2, 39, 5, 10, 8];
+ let ResourceCycles = [2, 39, 5, 10, 8];
let Latency = 62;
let NumMicroOps = 64;
}
def : InstRW<[ADLPWriteResGroup59], (instrs FLDENVm)>;
def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06]> {
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let Latency = 4;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup60], (instrs FNCLEX)>;
def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
- let ReleaseAtCycles = [6, 3, 6];
+ let ResourceCycles = [6, 3, 6];
let Latency = 75;
let NumMicroOps = 15;
}
@@ -976,28 +976,28 @@ def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort0
def : InstRW<[ADLPWriteResGroup64], (instrs FNSTSWm)>;
def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
- let ReleaseAtCycles = [9, 30, 21, 1, 11, 11, 16, 1];
+ let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
let Latency = 106;
let NumMicroOps = 100;
}
def : InstRW<[ADLPWriteResGroup65], (instrs FSTENVm)>;
def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
- let ReleaseAtCycles = [4, 47, 1, 2, 1, 33, 2];
+ let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
let Latency = 63;
let NumMicroOps = 90;
}
def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR)>;
def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
- let ReleaseAtCycles = [4, 45, 1, 2, 1, 31, 4];
+ let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
let Latency = 63;
let NumMicroOps = 88;
}
def : InstRW<[ADLPWriteResGroup67], (instrs FXRSTOR64)>;
def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+ let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 110;
}
@@ -1019,41 +1019,41 @@ def : InstRW<[ADLPWriteResGroup70], (instregex "^(V?)GF2P8MULBrr$")>;
def : InstRW<[ADLPWriteResGroup70], (instrs VGF2P8MULBYrr)>;
def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
+ let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[ADLPWriteResGroup71], (instrs IN16ri)>;
def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
+ let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[ADLPWriteResGroup72], (instrs IN16rr)>;
def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
+ let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
let Latency = 35;
let NumMicroOps = 94;
}
def : InstRW<[ADLPWriteResGroup73], (instrs IN32ri)>;
def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
+ let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
let NumMicroOps = 99;
}
def : InstRW<[ADLPWriteResGroup74], (instrs IN32rr)>;
def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
+ let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[ADLPWriteResGroup75], (instrs IN8ri)>;
def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
+ let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
let Latency = 35;
let NumMicroOps = 86;
}
@@ -1073,28 +1073,28 @@ def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,
VBROADCASTSSrm)>;
def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
+ let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 83;
}
def : InstRW<[ADLPWriteResGroup79], (instrs INSB)>;
def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
+ let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
let Latency = 20;
let NumMicroOps = 92;
}
def : InstRW<[ADLPWriteResGroup80], (instrs INSL)>;
def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
+ let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 86;
}
def : InstRW<[ADLPWriteResGroup81], (instrs INSW)>;
def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
+ let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 42;
}
@@ -1124,35 +1124,35 @@ def : InstRW<[ADLPWriteResGroup86], (instregex "^JMP_(1|4)$")>;
def : InstRW<[ADLPWriteResGroup86], (instrs VZEROUPPER)>;
def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [8, 2, 14, 3, 1];
+ let ResourceCycles = [8, 2, 14, 3, 1];
let Latency = 198;
let NumMicroOps = 81;
}
def : InstRW<[ADLPWriteResGroup87], (instrs LAR16rm)>;
def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 66;
let NumMicroOps = 22;
}
def : InstRW<[ADLPWriteResGroup88], (instrs LAR16rr)>;
def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 85;
}
def : InstRW<[ADLPWriteResGroup89], (instrs LAR32rm)>;
def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 65;
let NumMicroOps = 22;
}
def : InstRW<[ADLPWriteResGroup90], (instregex "^LAR(32|64)rr$")>;
def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 87;
}
@@ -1170,7 +1170,7 @@ def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
def : InstRW<[ADLPWriteResGroup93], (instrs LEA16r)>;
def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 6;
let NumMicroOps = 4;
}
@@ -1179,77 +1179,77 @@ def : InstRW<[ADLPWriteResGroup94], (instregex "^LODS(B|W)$",
def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE)>;
def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup95], (instrs LEAVE64)>;
def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
+ let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
def : InstRW<[ADLPWriteResGroup96], (instrs LGDT64m)>;
def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
+ let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
def : InstRW<[ADLPWriteResGroup97], (instrs LIDT64m)>;
def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [5, 3, 2, 1, 1];
+ let ResourceCycles = [5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 12;
}
def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16m)>;
def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
+ let ResourceCycles = [1, 4, 3, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 11;
}
def : InstRW<[ADLPWriteResGroup99], (instrs LLDT16r)>;
def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
+ let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 27;
}
def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16m)>;
def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
+ let ResourceCycles = [5, 7, 1, 2, 5, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 22;
}
def : InstRW<[ADLPWriteResGroup101], (instrs LMSW16r)>;
def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 5;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup102], (instregex "^LODS(L|Q)$")>;
def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [2, 4, 1];
+ let ResourceCycles = [2, 4, 1];
let Latency = 3;
let NumMicroOps = 7;
}
def : InstRW<[ADLPWriteResGroup103], (instrs LOOP)>;
def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [4, 6, 1];
+ let ResourceCycles = [4, 6, 1];
let Latency = 3;
let NumMicroOps = 11;
}
def : InstRW<[ADLPWriteResGroup104], (instrs LOOPE)>;
def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [4, 6, 1];
+ let ResourceCycles = [4, 6, 1];
let Latency = 2;
let NumMicroOps = 11;
}
@@ -1262,14 +1262,14 @@ def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, AD
def : InstRW<[ADLPWriteResGroup106], (instrs LRET64)>;
def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 5, 3, 3, 1];
+ let ResourceCycles = [1, 5, 3, 3, 1];
let Latency = 70;
let NumMicroOps = 13;
}
def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rm$")>;
def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
+ let ResourceCycles = [1, 4, 4, 3, 2, 1];
let Latency = 63;
let NumMicroOps = 15;
}
@@ -1312,7 +1312,7 @@ def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 12;
let NumMicroOps = 4;
}
@@ -1347,7 +1347,7 @@ def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 12;
let NumMicroOps = 3;
}
@@ -1355,7 +1355,7 @@ def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|
def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
@@ -1370,14 +1370,14 @@ def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 11;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 3;
let NumMicroOps = 3;
}
@@ -1434,7 +1434,7 @@ def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort02_03_11]> {
def : InstRW<[ADLPWriteResGroup132], (instrs MOV64ao32)>;
def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
+ let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
let Latency = 217;
let NumMicroOps = 48;
}
@@ -1453,7 +1453,7 @@ def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06,
def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rc)>;
def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
- let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
+ let ResourceCycles = [3, 4, 8, 4, 2, 3];
let Latency = 181;
let NumMicroOps = 24;
}
@@ -1541,7 +1541,7 @@ def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
def : InstRW<[ADLPWriteResGroup149], (instrs MOVNTImr)>;
def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [4, 1, 1, 1];
+ let ResourceCycles = [4, 1, 1, 1];
let Latency = 8;
let NumMicroOps = 7;
}
@@ -1554,7 +1554,7 @@ def : InstRW<[ADLPWriteResGroup151], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
def : InstRW<[ADLPWriteResGroup151], (instrs VPBLENDDrri)>;
def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [4, 1, 1, 1];
+ let ResourceCycles = [4, 1, 1, 1];
let Latency = 7;
let NumMicroOps = 7;
}
@@ -1596,70 +1596,70 @@ def : InstRW<[ADLPWriteResGroup158], (instregex "^MUL_F(P?)rST0$")>;
def : InstRW<[ADLPWriteResGroup158], (instrs MUL_FST0r)>;
def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
- let ReleaseAtCycles = [7, 1, 2];
+ let ResourceCycles = [7, 1, 2];
let Latency = 20;
let NumMicroOps = 10;
}
def : InstRW<[ADLPWriteResGroup159], (instrs MWAITrr)>;
def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
+ let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
def : InstRW<[ADLPWriteResGroup160], (instrs OUT16ir)>;
def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
+ let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
def : InstRW<[ADLPWriteResGroup161], (instrs OUT16rr)>;
def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
+ let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
def : InstRW<[ADLPWriteResGroup162], (instrs OUT32ir)>;
def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
+ let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
def : InstRW<[ADLPWriteResGroup163], (instrs OUT32rr)>;
def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
+ let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
def : InstRW<[ADLPWriteResGroup164], (instrs OUT8ir)>;
def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
+ let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
def : InstRW<[ADLPWriteResGroup165], (instrs OUT8rr)>;
def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
+ let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 80;
}
def : InstRW<[ADLPWriteResGroup166], (instrs OUTSB)>;
def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
+ let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 89;
}
def : InstRW<[ADLPWriteResGroup167], (instrs OUTSL)>;
def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
+ let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 83;
}
@@ -1718,14 +1718,14 @@ def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort
def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PEXTR(D|Q)mr$")>;
def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 9;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup177, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 2;
let NumMicroOps = 3;
}
@@ -1747,14 +1747,14 @@ def : InstRW<[ADLPWriteResGroup180], (instregex "^POPA(16|32)$",
def : InstRW<[ADLPWriteResGroup180], (instrs POPF32)>;
def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [6, 2, 1, 1];
+ let ResourceCycles = [6, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 10;
}
def : InstRW<[ADLPWriteResGroup181], (instrs POPF16)>;
def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
@@ -1767,21 +1767,21 @@ def : InstRW<[ADLPWriteResGroup183], (instregex "^PREFETCHT(0|1|2)$")>;
def : InstRW<[ADLPWriteResGroup183], (instrs PREFETCHNTA)>;
def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITE((64)?)m$")>;
def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITE64r)>;
def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
@@ -1814,49 +1814,49 @@ def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_
def : InstRW<[ADLPWriteResGroup191], (instregex "^PUSH(F|G)S64$")>;
def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [2, 3, 2];
+ let ResourceCycles = [2, 3, 2];
let Latency = 8;
let NumMicroOps = 7;
}
def : InstRW<[ADLPWriteResGroup192], (instregex "^RC(L|R)(16|32|64)rCL$")>;
def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [1, 5, 2];
+ let ResourceCycles = [1, 5, 2];
let Latency = 20;
let NumMicroOps = 8;
}
def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instrs RCL8mCL)>;
def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [2, 5, 2];
+ let ResourceCycles = [2, 5, 2];
let Latency = 7;
let NumMicroOps = 9;
}
def : InstRW<[ADLPWriteResGroup195], (instrs RCL8rCL)>;
def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [2, 4, 3];
+ let ResourceCycles = [2, 4, 3];
let Latency = 20;
let NumMicroOps = 9;
}
def : InstRW<[ADLPWriteResGroup196, WriteRMW], (instrs RCR8mCL)>;
def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [3, 4, 3];
+ let ResourceCycles = [3, 4, 3];
let Latency = 9;
let NumMicroOps = 10;
}
def : InstRW<[ADLPWriteResGroup197], (instrs RCR8rCL)>;
def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
- let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
+ let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 54;
}
@@ -1874,49 +1874,49 @@ def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06,
def : InstRW<[ADLPWriteResGroup200], (instrs RDPKRUr)>;
def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
- let ReleaseAtCycles = [9, 6, 2, 1];
+ let ResourceCycles = [9, 6, 2, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 18;
}
def : InstRW<[ADLPWriteResGroup201], (instrs RDPMC)>;
def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = 1386;
let NumMicroOps = 25;
}
def : InstRW<[ADLPWriteResGroup202], (instrs RDRAND16r)>;
def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
def : InstRW<[ADLPWriteResGroup203], (instregex "^RDRAND(32|64)r$")>;
def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = 1381;
let NumMicroOps = 25;
}
def : InstRW<[ADLPWriteResGroup204], (instrs RDSEED16r)>;
def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
def : InstRW<[ADLPWriteResGroup205], (instregex "^RDSEED(32|64)r$")>;
def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
- let ReleaseAtCycles = [5, 6, 3, 1];
+ let ResourceCycles = [5, 6, 3, 1];
let Latency = 18;
let NumMicroOps = 15;
}
def : InstRW<[ADLPWriteResGroup206], (instrs RDTSC)>;
def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
- let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
+ let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
let Latency = 42;
let NumMicroOps = 21;
}
@@ -1929,7 +1929,7 @@ def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
def : InstRW<[ADLPWriteResGroup208], (instrs RET64)>;
def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
@@ -1939,20 +1939,20 @@ def ADLPWriteResGroup210 : SchedWriteRes<[]>;
def : InstRW<[ADLPWriteResGroup210], (instrs REX64_PREFIX)>;
def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
@@ -1961,7 +1961,7 @@ def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
"^(RO|SA|SH)R8mCL$")>;
def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
@@ -1987,7 +1987,7 @@ def : InstRW<[ADLPWriteResGroup217], (instregex "^S(A|H)RX(32|64)rr$",
"^SHLX(32|64)rr$")>;
def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 2, 1, 1, 1];
+ let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 7;
}
@@ -2000,7 +2000,7 @@ def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
def : InstRW<[ADLPWriteResGroup219], (instrs SFENCE)>;
def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 2, 2, 2];
+ let ResourceCycles = [1, 2, 2, 2];
let Latency = 21;
let NumMicroOps = 7;
}
@@ -2019,14 +2019,14 @@ def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
def : InstRW<[ADLPWriteResGroup222], (instrs SHA1MSG1rr)>;
def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 2, 1, 2, 1];
+ let ResourceCycles = [2, 2, 1, 2, 1];
let Latency = 13;
let NumMicroOps = 8;
}
def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
- let ReleaseAtCycles = [2, 2, 1, 2];
+ let ResourceCycles = [2, 2, 1, 2];
let Latency = 6;
let NumMicroOps = 7;
}
@@ -2058,28 +2058,28 @@ def : InstRW<[ADLPWriteResGroup228], (instrs SHA1RNDS4rri,
SHA256RNDS2rr)>;
def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [3, 2, 1, 1, 1];
+ let ResourceCycles = [3, 2, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 8;
}
def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
- let ReleaseAtCycles = [3, 2, 1, 1];
+ let ResourceCycles = [3, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
def : InstRW<[ADLPWriteResGroup230], (instrs SHA256MSG1rr)>;
def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup231, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 6;
let NumMicroOps = 2;
}
@@ -2121,21 +2121,21 @@ def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]
def : InstRW<[ADLPWriteResGroup238], (instrs STD)>;
def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [1, 4, 1];
+ let ResourceCycles = [1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 6;
}
def : InstRW<[ADLPWriteResGroup239], (instrs STI)>;
def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 8;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup240], (instrs STOSB)>;
def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 7;
let NumMicroOps = 4;
}
@@ -2154,7 +2154,7 @@ def : InstRW<[ADLPWriteResGroup243], (instregex "^(TST|XAM)_F$")>;
def : InstRW<[ADLPWriteResGroup243], (instrs UCOM_FPPr)>;
def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 9;
let NumMicroOps = 4;
}
@@ -2162,7 +2162,7 @@ def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefaul
def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 3;
let NumMicroOps = 3;
}
@@ -2170,35 +2170,35 @@ def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rr$")>;
def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrr)>;
def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [6, 7, 18];
+ let ResourceCycles = [6, 7, 18];
let Latency = 81;
let NumMicroOps = 31;
}
def : InstRW<[ADLPWriteResGroup246], (instrs VERRm)>;
def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [6, 7, 17];
+ let ResourceCycles = [6, 7, 17];
let Latency = 74;
let NumMicroOps = 30;
}
def : InstRW<[ADLPWriteResGroup247], (instrs VERRr)>;
def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [5, 8, 21];
+ let ResourceCycles = [5, 8, 21];
let Latency = 81;
let NumMicroOps = 34;
}
def : InstRW<[ADLPWriteResGroup248], (instrs VERWm)>;
def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [5, 8, 20];
+ let ResourceCycles = [5, 8, 20];
let Latency = 74;
let NumMicroOps = 33;
}
def : InstRW<[ADLPWriteResGroup249], (instrs VERWr)>;
def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 4];
+ let ResourceCycles = [1, 1, 2, 4];
let Latency = 29;
let NumMicroOps = 8;
}
@@ -2208,7 +2208,7 @@ def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGAT
VPGATHERQDYrm)>;
def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 1, 2];
+ let ResourceCycles = [1, 1, 1, 2];
let Latency = 20;
let NumMicroOps = 5;
}
@@ -2218,7 +2218,7 @@ def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGAT
VPGATHERQDrm)>;
def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 8];
+ let ResourceCycles = [1, 1, 2, 8];
let Latency = 30;
let NumMicroOps = 12;
}
@@ -2226,7 +2226,7 @@ def : InstRW<[ADLPWriteResGroup252, WriteVecMaskedGatherWriteback], (instrs VGAT
VPGATHERDDYrm)>;
def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 4];
+ let ResourceCycles = [1, 1, 2, 4];
let Latency = 28;
let NumMicroOps = 8;
}
@@ -2234,7 +2234,7 @@ def : InstRW<[ADLPWriteResGroup253, WriteVecMaskedGatherWriteback], (instrs VGAT
VPGATHERDDrm)>;
def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 5;
let NumMicroOps = 3;
}
@@ -2254,7 +2254,7 @@ def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_
def : InstRW<[ADLPWriteResGroup256], (instrs VLDMXCSR)>;
def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
- let ReleaseAtCycles = [8, 1, 1, 1, 1, 1, 2, 3];
+ let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
let Latency = 40;
let NumMicroOps = 18;
}
@@ -2305,98 +2305,98 @@ def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yr
def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 10;
let NumMicroOps = 4;
}
def : InstRW<[ADLPWriteResGroup266, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
- let ReleaseAtCycles = [1, 2, 3, 3, 1];
+ let ResourceCycles = [1, 2, 3, 3, 1];
let Latency = 16;
let NumMicroOps = 10;
}
def : InstRW<[ADLPWriteResGroup267], (instrs VZEROALL)>;
def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup268], (instrs WAIT)>;
def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+ let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 144;
}
def : InstRW<[ADLPWriteResGroup269], (instrs WRMSR)>;
def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
- let ReleaseAtCycles = [2, 1, 4, 1];
+ let ResourceCycles = [2, 1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 8;
}
def : InstRW<[ADLPWriteResGroup270], (instrs WRPKRUr)>;
def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XADD8rm)>;
def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
- let ReleaseAtCycles = [4, 1];
+ let ResourceCycles = [4, 1];
let Latency = 39;
let NumMicroOps = 5;
}
def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
- let ReleaseAtCycles = [5, 1];
+ let ResourceCycles = [5, 1];
let Latency = 39;
let NumMicroOps = 6;
}
def : InstRW<[ADLPWriteResGroup274, WriteRMW], (instrs XCHG64rm)>;
def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
- let ReleaseAtCycles = [4, 1];
+ let ResourceCycles = [4, 1];
let Latency = 40;
let NumMicroOps = 5;
}
def : InstRW<[ADLPWriteResGroup275, WriteRMW], (instrs XCHG8rm)>;
def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
- let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
+ let ResourceCycles = [2, 4, 2, 1, 2, 4];
let Latency = 17;
let NumMicroOps = 15;
}
def : InstRW<[ADLPWriteResGroup276], (instrs XCH_F)>;
def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
- let ReleaseAtCycles = [7, 3, 8, 5];
+ let ResourceCycles = [7, 3, 8, 5];
let Latency = 4;
let NumMicroOps = 23;
}
def : InstRW<[ADLPWriteResGroup277], (instrs XGETBV)>;
def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 7;
let NumMicroOps = 3;
}
def : InstRW<[ADLPWriteResGroup278], (instrs XLAT)>;
def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
- let ReleaseAtCycles = [21, 1, 1, 8];
+ let ResourceCycles = [21, 1, 1, 8];
let Latency = 37;
let NumMicroOps = 31;
}
@@ -2404,63 +2404,63 @@ def : InstRW<[ADLPWriteResGroup279], (instregex "^XRSTOR((S|64)?)$")>;
def : InstRW<[ADLPWriteResGroup279], (instrs XRSTORS64)>;
def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 42;
let NumMicroOps = 140;
}
def : InstRW<[ADLPWriteResGroup280], (instrs XSAVE)>;
def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 41;
let NumMicroOps = 140;
}
def : InstRW<[ADLPWriteResGroup281], (instrs XSAVE64)>;
def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+ let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 151;
}
def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEC)>;
def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+ let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 152;
}
def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEC64)>;
def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+ let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 155;
}
def : InstRW<[ADLPWriteResGroup284], (instrs XSAVEOPT)>;
def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+ let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 156;
}
def : InstRW<[ADLPWriteResGroup285], (instrs XSAVEOPT64)>;
def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+ let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
let Latency = 42;
let NumMicroOps = 184;
}
def : InstRW<[ADLPWriteResGroup286], (instrs XSAVES)>;
def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+ let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
let Latency = 42;
let NumMicroOps = 186;
}
def : InstRW<[ADLPWriteResGroup287], (instrs XSAVES64)>;
def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
- let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
+ let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
let Latency = 5;
let NumMicroOps = 54;
}
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 8575f747b4d3bc..a9639e77712ef3 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -95,7 +95,7 @@ multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -103,7 +103,7 @@ multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -489,7 +489,7 @@ defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
def : WriteRes<WriteVecInsert, [BWPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
let Latency = 6;
@@ -511,48 +511,48 @@ def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
def : WriteRes<WritePCmpIStrM, [BWPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
let Latency = 24;
let NumMicroOps = 10;
- let ReleaseAtCycles = [4,3,1,1,1];
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [BWPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4,3,1];
+ let ResourceCycles = [4,3,1];
}
def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
let Latency = 23;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
// MOVMSK Instructions.
@@ -565,41 +565,41 @@ def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
let Latency = 14;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
let Latency = 19;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
let Latency = 29;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,7,2];
+ let ResourceCycles = [2,7,2];
}
def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
let Latency = 33;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,7,1,1];
+ let ResourceCycles = [2,7,1,1];
}
// Carry-less multiplication instructions.
defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
// Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
// Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; }
@@ -628,7 +628,7 @@ defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
"VPSRLVQ(Y?)rr")>;
@@ -636,7 +636,7 @@ def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
"UCOM_F(P?)r")>;
@@ -644,49 +644,49 @@ def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
SIDT64m,
@@ -697,7 +697,7 @@ def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
@@ -705,14 +705,14 @@ def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
MFENCE,
@@ -722,28 +722,28 @@ def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup20], (instrs CWD,
JCXZ, JECXZ, JRCXZ,
@@ -755,21 +755,21 @@ def: InstRW<[BWWriteResGroup20], (instrs CWD,
def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
STOSB, STOSL, STOSQ, STOSW)>;
@@ -778,14 +778,14 @@ def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr")>;
def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
VPBROADCASTWrr)>;
@@ -793,7 +793,7 @@ def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -802,14 +802,14 @@ def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr,
def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -817,28 +817,28 @@ def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 5;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
@@ -846,28 +846,28 @@ def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr")>;
def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
"IST_F(16|32)m")>;
@@ -875,28 +875,28 @@ def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
def BWWriteResGroup46 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
VMOVDDUPrm, MOVDDUPrm,
@@ -908,42 +908,42 @@ def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,4];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
@@ -959,14 +959,14 @@ def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup59], (instrs VPSLLVQrm, VPSRLVQrm)>;
def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>;
def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
@@ -974,7 +974,7 @@ def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
"MOVBE(16|32|64)rm")>;
@@ -982,7 +982,7 @@ def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
VINSERTI128rm,
@@ -991,7 +991,7 @@ def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
@@ -999,14 +999,14 @@ def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -1015,7 +1015,7 @@ def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
@@ -1023,14 +1023,14 @@ def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,5];
+ let ResourceCycles = [1,5];
}
def: InstRW<[BWWriteResGroup71], (instrs STD)>;
def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
VPSRLVQYrm)>;
@@ -1038,21 +1038,21 @@ def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm,
MMX_PACKSSWBrm,
@@ -1061,7 +1061,7 @@ def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm,
def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
@@ -1069,21 +1069,21 @@ def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>;
def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -1091,7 +1091,7 @@ def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
@@ -1099,14 +1099,14 @@ def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,1,1];
+ let ResourceCycles = [1,1,1,1,1];
}
def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>;
@@ -1114,21 +1114,21 @@ def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>;
def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,2,1,2];
+ let ResourceCycles = [2,2,1,2];
}
def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
VPMOVSXBQYrm,
@@ -1141,7 +1141,7 @@ def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
"RCR(8|16|32|64)m(1|i)")>;
@@ -1149,14 +1149,14 @@ def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,3];
+ let ResourceCycles = [1,1,1,3];
}
def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,2,1];
}
def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
@@ -1168,7 +1168,7 @@ def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
@@ -1176,7 +1176,7 @@ def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
let Latency = 9;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
"VPBROADCASTW(Y?)rm")>;
@@ -1184,14 +1184,14 @@ def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,3];
+ let ResourceCycles = [1,1,3];
}
def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
"LSL(16|32|64)rm")>;
@@ -1199,28 +1199,28 @@ def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1,3]; // Really 2.5 cycle throughput
+ let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
}
def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
@@ -1228,7 +1228,7 @@ def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,2,3];
+ let ResourceCycles = [2,2,3];
}
def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
"RCR(16|32|64)rCL")>;
@@ -1236,14 +1236,14 @@ def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,4,1,3];
+ let ResourceCycles = [1,4,1,3];
}
def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,9];
+ let ResourceCycles = [2,9];
}
def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
@@ -1251,84 +1251,84 @@ def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
let Latency = 14;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,2,1,3];
+ let ResourceCycles = [2,2,1,3];
}
def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
- let ReleaseAtCycles = [2,3,1,4];
+ let ResourceCycles = [2,3,1,4];
}
def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
let Latency = 14;
let NumMicroOps = 12;
- let ReleaseAtCycles = [2,1,4,5];
+ let ResourceCycles = [2,1,4,5];
}
def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
let Latency = 15;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
let Latency = 15;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,1,1,4,1,2];
+ let ResourceCycles = [1,1,1,4,1,2];
}
def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1,5];
+ let ResourceCycles = [1,1,5];
}
def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,1,1,4,2,5];
+ let ResourceCycles = [1,1,1,4,2,5];
}
def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
let Latency = 8;
let NumMicroOps = 20;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,5];
+ let ResourceCycles = [1,1,1,5];
}
def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
@@ -1336,84 +1336,84 @@ def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
let Latency = 18;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,1,1,3,1,3];
+ let ResourceCycles = [2,1,1,3,1,3];
}
def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 19;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1,8];
+ let ResourceCycles = [1,1,8];
}
def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
let Latency = 20;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 20;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,1,2];
+ let ResourceCycles = [1,1,1,1,1,1,2];
}
def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 21;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 21;
let NumMicroOps = 19;
- let ReleaseAtCycles = [2,1,4,1,1,4,6];
+ let ResourceCycles = [2,1,4,1,1,4,6];
}
def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 22;
let NumMicroOps = 18;
- let ReleaseAtCycles = [1,1,16];
+ let ResourceCycles = [1,1,16];
}
def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
- let ReleaseAtCycles = [3,1,15];
+ let ResourceCycles = [3,1,15];
}
def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 24;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 26;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let Latency = 29;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
let Latency = 17;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,3,2,1];
+ let ResourceCycles = [1,3,2,1];
}
def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm,
VGATHERQPDrm, VPGATHERQQrm)>;
@@ -1421,7 +1421,7 @@ def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm,
def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
let Latency = 18;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,3,4,1];
+ let ResourceCycles = [1,3,4,1];
}
def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
VGATHERQPDYrm, VPGATHERQQYrm)>;
@@ -1429,14 +1429,14 @@ def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,5,2,1];
+ let ResourceCycles = [1,5,2,1];
}
def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
let Latency = 19;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,4,4,1];
+ let ResourceCycles = [1,4,4,1];
}
def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm,
VGATHERQPSYrm, VPGATHERQDYrm)>;
@@ -1444,21 +1444,21 @@ def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm,
def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
let Latency = 21;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,4,8,1];
+ let ResourceCycles = [1,4,8,1];
}
def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
let Latency = 29;
let NumMicroOps = 27;
- let ReleaseAtCycles = [1,5,1,1,19];
+ let ResourceCycles = [1,5,1,1,19];
}
def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
let Latency = 30;
let NumMicroOps = 28;
- let ReleaseAtCycles = [1,6,1,1,19];
+ let ResourceCycles = [1,6,1,1,19];
}
def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
@@ -1466,7 +1466,7 @@ def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
let Latency = 34;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,3,4,10];
+ let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
"IN(8|16|32)rr")>;
@@ -1474,7 +1474,7 @@ def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,2,1,4,10];
+ let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
@@ -1482,42 +1482,42 @@ def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
let Latency = 42;
let NumMicroOps = 22;
- let ReleaseAtCycles = [2,20];
+ let ResourceCycles = [2,20];
}
def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
let Latency = 60;
let NumMicroOps = 64;
- let ReleaseAtCycles = [2,2,8,1,10,2,39];
+ let ResourceCycles = [2,2,8,1,10,2,39];
}
def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
let Latency = 63;
let NumMicroOps = 88;
- let ReleaseAtCycles = [4,4,31,1,2,1,45];
+ let ResourceCycles = [4,4,31,1,2,1,45];
}
def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
let Latency = 63;
let NumMicroOps = 90;
- let ReleaseAtCycles = [4,2,33,1,2,1,47];
+ let ResourceCycles = [4,2,33,1,2,1,47];
}
def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
- let ReleaseAtCycles = [6,3,6];
+ let ResourceCycles = [6,3,6];
}
def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
let Latency = 115;
let NumMicroOps = 100;
- let ReleaseAtCycles = [9,9,11,8,1,11,21,30];
+ let ResourceCycles = [9,9,11,8,1,11,21,30];
}
def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
@@ -1596,7 +1596,7 @@ def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -1610,13 +1610,13 @@ def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
// CMOVs that use both Z and C flag require an extra uop.
def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
let NumMicroOps = 2;
}
def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
let Latency = 7;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
let NumMicroOps = 3;
}
@@ -1636,13 +1636,13 @@ def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
let NumMicroOps = 2;
}
def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index d10d7684ac1273..d871ef4c353eff 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -100,7 +100,7 @@ multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -108,7 +108,7 @@ multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -488,7 +488,7 @@ defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; //
def : WriteRes<WriteVecInsert, [HWPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
let Latency = 6;
@@ -511,48 +511,48 @@ def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
def : WriteRes<WritePCmpIStrM, [HWPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
let Latency = 17;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
let Latency = 25;
let NumMicroOps = 10;
- let ReleaseAtCycles = [4,3,1,1,1];
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [HWPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
let Latency = 17;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4,3,1];
+ let ResourceCycles = [4,3,1];
}
def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
let Latency = 24;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
// MOVMSK Instructions.
@@ -565,51 +565,51 @@ def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; }
def : WriteRes<WriteAESDecEnc, [HWPort5]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
let Latency = 13;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [HWPort5]> {
let Latency = 14;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
let Latency = 20;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
let Latency = 29;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,7,2];
+ let ResourceCycles = [2,7,2];
}
def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
let Latency = 34;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,7,1,1];
+ let ResourceCycles = [2,7,1,1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
let Latency = 17;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
// Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
// Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
@@ -655,7 +655,7 @@ def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
let NumMicroOps = 3;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
}
// Starting with P1.
@@ -664,7 +664,7 @@ def HWWriteP1 : SchedWriteRes<[HWPort1]>;
def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// Notation:
@@ -713,7 +713,7 @@ def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;
// i.
def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
let NumMicroOps = 4;
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
}
def : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>;
@@ -742,7 +742,7 @@ def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
}
def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
@@ -750,7 +750,7 @@ def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
let Latency = 4;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2, 3];
+ let ResourceCycles = [2, 3];
}
def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
@@ -765,7 +765,7 @@ def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
// RDRAND.
def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
let NumMicroOps = 17;
- let ReleaseAtCycles = [1, 16];
+ let ResourceCycles = [1, 16];
}
def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
@@ -863,7 +863,7 @@ def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;
def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
@@ -874,7 +874,7 @@ def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
VBROADCASTI128,
@@ -889,7 +889,7 @@ def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
let Latency = 1;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;
def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
@@ -897,7 +897,7 @@ def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
"VPSRLVQ(Y?)rr")>;
@@ -905,7 +905,7 @@ def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
"UCOM_F(P?)r")>;
@@ -913,49 +913,49 @@ def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup10], (instrs SGDT64m,
SIDT64m,
@@ -966,21 +966,21 @@ def: InstRW<[HWWriteResGroup10], (instrs SGDT64m,
def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;
def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSrm)>;
def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
@@ -988,7 +988,7 @@ def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
"(V?)PMOV(SX|ZX)BQrm",
@@ -1000,7 +1000,7 @@ def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
VPMOVSXBQYrm,
@@ -1009,7 +1009,7 @@ def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>;
def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
@@ -1017,7 +1017,7 @@ def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
"MOVBE(16|32|64)rm")>;
@@ -1025,7 +1025,7 @@ def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
VINSERTI128rm,
@@ -1034,14 +1034,14 @@ def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;
def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
@@ -1049,35 +1049,35 @@ def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
STOSB, STOSL, STOSQ, STOSW)>;
@@ -1086,7 +1086,7 @@ def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;
def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -1095,7 +1095,7 @@ def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
@@ -1103,14 +1103,14 @@ def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
MFENCE,
@@ -1120,28 +1120,28 @@ def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm,
MMX_PACKSSWBrm,
@@ -1150,7 +1150,7 @@ def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm,
def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
@@ -1158,35 +1158,35 @@ def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>;
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -1194,7 +1194,7 @@ def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
@@ -1202,14 +1202,14 @@ def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,1,1];
+ let ResourceCycles = [1,1,1,1,1];
}
def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;
@@ -1217,21 +1217,21 @@ def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;
def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr")>;
def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
@@ -1239,7 +1239,7 @@ def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
VPMOVSXDQYrm,
@@ -1249,7 +1249,7 @@ def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -1258,14 +1258,14 @@ def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr,
def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -1273,28 +1273,28 @@ def: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def HWWriteResGroup60 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
let Latency = 5;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[HWWriteResGroup60], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def HWWriteResGroup60b : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
let Latency = 6;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[HWWriteResGroup60b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
"IST_F(16|32)m")>;
@@ -1302,7 +1302,7 @@ def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
"RCR(8|16|32|64)m(1|i)")>;
@@ -1310,14 +1310,14 @@ def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,3];
+ let ResourceCycles = [1,1,1,3];
}
def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@@ -1329,14 +1329,14 @@ def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr,
MMX_CVTTPS2PIrr)>;
@@ -1344,49 +1344,49 @@ def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr,
def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let Latency = 9;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDrm)>;
def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
let Latency = 9;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
def HWWriteResGroup82 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
"LSL(16|32|64)rm")>;
@@ -1394,28 +1394,28 @@ def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,4];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;
def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
@@ -1423,77 +1423,77 @@ def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,5];
+ let ResourceCycles = [1,5];
}
def: InstRW<[HWWriteResGroup108], (instrs STD)>;
def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,2,1,2];
+ let ResourceCycles = [2,2,1,2];
}
def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
let Latency = 16;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,1,1,4,1,2];
+ let ResourceCycles = [1,1,1,4,1,2];
}
def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,2,3];
+ let ResourceCycles = [2,2,3];
}
def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
"RCR(16|32|64)rCL")>;
@@ -1501,140 +1501,140 @@ def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,4,1,3];
+ let ResourceCycles = [1,4,1,3];
}
def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;
def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,9];
+ let ResourceCycles = [2,9];
}
def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
let Latency = 17;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,1,1,4,2,5];
+ let ResourceCycles = [1,1,1,4,2,5];
}
def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
let Latency = 19;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,1,1,3,1,3];
+ let ResourceCycles = [2,1,1,3,1,3];
}
def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
- let ReleaseAtCycles = [2,3,1,4];
+ let ResourceCycles = [2,3,1,4];
}
def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;
def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
let Latency = 19;
let NumMicroOps = 15;
- let ReleaseAtCycles = [1,14];
+ let ResourceCycles = [1,14];
}
def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;
def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 21;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,1,2];
+ let ResourceCycles = [1,1,1,1,1,1,2];
}
def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
let Latency = 8;
let NumMicroOps = 20;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 22;
let NumMicroOps = 19;
- let ReleaseAtCycles = [2,1,4,1,1,4,6];
+ let ResourceCycles = [2,1,4,1,1,4,6];
}
def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
let Latency = 17;
let NumMicroOps = 15;
- let ReleaseAtCycles = [2,1,2,4,2,4];
+ let ResourceCycles = [2,1,2,4,2,4];
}
def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,5];
+ let ResourceCycles = [1,1,1,5];
}
def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
- let ReleaseAtCycles = [3,1,15];
+ let ResourceCycles = [3,1,15];
}
def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
let Latency = 20;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 27;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
let Latency = 20;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,2,7];
+ let ResourceCycles = [1,2,7];
}
def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let Latency = 30;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
let Latency = 24;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 31;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
let Latency = 30;
let NumMicroOps = 27;
- let ReleaseAtCycles = [1,5,1,1,19];
+ let ResourceCycles = [1,5,1,1,19];
}
def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
let Latency = 31;
let NumMicroOps = 28;
- let ReleaseAtCycles = [1,6,1,1,19];
+ let ResourceCycles = [1,6,1,1,19];
}
def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
@@ -1642,14 +1642,14 @@ def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let Latency = 34;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,3,4,10];
+ let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
"IN(8|16|32)rr")>;
@@ -1657,7 +1657,7 @@ def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 36;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,2,1,4,10];
+ let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
@@ -1665,91 +1665,91 @@ def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
let Latency = 41;
let NumMicroOps = 18;
- let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
+ let ResourceCycles = [1,1,2,3,1,1,1,8];
}
def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
let Latency = 42;
let NumMicroOps = 22;
- let ReleaseAtCycles = [2,20];
+ let ResourceCycles = [2,20];
}
def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
let Latency = 61;
let NumMicroOps = 64;
- let ReleaseAtCycles = [2,2,8,1,10,2,39];
+ let ResourceCycles = [2,2,8,1,10,2,39];
}
def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
let Latency = 64;
let NumMicroOps = 88;
- let ReleaseAtCycles = [4,4,31,1,2,1,45];
+ let ResourceCycles = [4,4,31,1,2,1,45];
}
def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
let Latency = 64;
let NumMicroOps = 90;
- let ReleaseAtCycles = [4,2,33,1,2,1,47];
+ let ResourceCycles = [4,2,33,1,2,1,47];
}
def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
- let ReleaseAtCycles = [6,3,6];
+ let ResourceCycles = [6,3,6];
}
def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
let Latency = 115;
let NumMicroOps = 100;
- let ReleaseAtCycles = [9,9,11,8,1,11,21,30];
+ let ResourceCycles = [9,9,11,8,1,11,21,30];
}
def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 14;
let NumMicroOps = 12;
- let ReleaseAtCycles = [2,2,2,1,3,2];
+ let ResourceCycles = [2,2,2,1,3,2];
}
def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>;
def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 17;
let NumMicroOps = 20;
- let ReleaseAtCycles = [3,3,4,1,5,4];
+ let ResourceCycles = [3,3,4,1,5,4];
}
def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>;
def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 16;
let NumMicroOps = 20;
- let ReleaseAtCycles = [3,3,4,1,5,4];
+ let ResourceCycles = [3,3,4,1,5,4];
}
def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>;
def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 22;
let NumMicroOps = 34;
- let ReleaseAtCycles = [5,3,8,1,9,8];
+ let ResourceCycles = [5,3,8,1,9,8];
}
def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 15;
let NumMicroOps = 14;
- let ReleaseAtCycles = [3,3,2,1,3,2];
+ let ResourceCycles = [3,3,2,1,3,2];
}
def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>;
def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 17;
let NumMicroOps = 22;
- let ReleaseAtCycles = [5,3,4,1,5,4];
+ let ResourceCycles = [5,3,4,1,5,4];
}
def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,
VGATHERQPSYrm, VPGATHERQDYrm)>;
@@ -1757,7 +1757,7 @@ def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,
def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
let Latency = 16;
let NumMicroOps = 15;
- let ReleaseAtCycles = [3,3,2,1,4,2];
+ let ResourceCycles = [3,3,2,1,4,2];
}
def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
@@ -1836,7 +1836,7 @@ def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -1866,7 +1866,7 @@ def HWFastADC0 : MCSchedPredicate<
def HWWriteADC0 : SchedWriteRes<[HWPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def HWWriteADC : SchedWriteVariant<[
@@ -1880,13 +1880,13 @@ def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,
// CMOVs that use both Z and C flag require an extra uop.
def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
let NumMicroOps = 3;
}
def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let Latency = 8;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}
@@ -1906,13 +1906,13 @@ def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
let NumMicroOps = 2;
}
def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index e5be73d22c40b6..283995f8203b0f 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -101,7 +101,7 @@ multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -109,7 +109,7 @@ multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -432,7 +432,7 @@ defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>;
def : WriteRes<WriteVecInsert, [ICXPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> {
let Latency = 6;
@@ -497,48 +497,48 @@ defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort49,ICXPort5,ICXPort78,ICXPort05], 8
def : WriteRes<WritePCmpIStrM, [ICXPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> {
let Latency = 25;
let NumMicroOps = 10;
- let ReleaseAtCycles = [4,3,1,1,1];
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [ICXPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4,3,1];
+ let ResourceCycles = [4,3,1];
}
def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> {
let Latency = 24;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
// MOVMSK Instructions.
@@ -551,46 +551,46 @@ def : WriteRes<WriteMMXMOVMSK, [ICXPort0]> { let Latency = 2; }
def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption.
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn.
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation.
let Latency = 20;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,2];
+ let ResourceCycles = [3,6,2];
}
def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> {
let Latency = 25;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,1,1];
+ let ResourceCycles = [3,6,1,1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [ICXPort5]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
// Catch-all for expensive system instructions.
@@ -610,8 +610,8 @@ def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def Wri
def : WriteRes<WriteFence, [ICXPort78, ICXPort49]>;
// Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [ICXPort49,ICXPort5,ICXPort78]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [ICXPort49,ICXPort5,ICXPort78]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -631,7 +631,7 @@ defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>;
def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
"KANDN(B|D|Q|W)rr",
@@ -659,7 +659,7 @@ def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r",
"KMOV(B|D|Q|W)kr",
@@ -676,35 +676,35 @@ def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r",
def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>;
def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
"VBLENDMPS(Z128|Z256)rr",
@@ -723,7 +723,7 @@ def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup10], (instrs SGDT64m,
SIDT64m,
@@ -734,7 +734,7 @@ def: InstRW<[ICXWriteResGroup10], (instrs SGDT64m,
def ICXWriteResGroup11 : SchedWriteRes<[ICXPort49,ICXPort78]> {
let Latency = 1;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
@@ -743,14 +743,14 @@ def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP,
MMX_MOVDQ2Qrr)>;
@@ -758,7 +758,7 @@ def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP,
def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup17], (instrs LFENCE,
WAIT,
@@ -767,21 +767,21 @@ def: InstRW<[ICXWriteResGroup17], (instrs LFENCE,
def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>;
def ICXWriteResGroup21 : SchedWriteRes<[ICXPort49,ICXPort78]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>;
def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup23], (instrs CWD,
JCXZ, JECXZ, JRCXZ,
@@ -793,21 +793,21 @@ def: InstRW<[ICXWriteResGroup23], (instrs CWD,
def ICXWriteResGroup25 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort78]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>;
def ICXWriteResGroup27 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort15]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
def ICXWriteResGroup28 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
STOSB, STOSL, STOSQ, STOSW)>;
@@ -816,14 +816,14 @@ def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
def ICXWriteResGroup29 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort15]> {
let Latency = 2;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2,2,1];
+ let ResourceCycles = [2,2,1];
}
def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
"KORTEST(B|D|Q|W)rr",
@@ -832,7 +832,7 @@ def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr",
"PEXT(32|64)rr")>;
@@ -840,7 +840,7 @@ def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr",
def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
"VALIGND(Z|Z128|Z256)rri",
@@ -852,7 +852,7 @@ def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0
def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
"KSHIFTL(B|D|Q|W)ri",
@@ -875,28 +875,28 @@ def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>;
def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -905,21 +905,21 @@ def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr,
def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>;
def ICXWriteResGroup43 : SchedWriteRes<[ICXPort49,ICXPort78]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -927,49 +927,49 @@ def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
let Latency = 5;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,3,2];
+ let ResourceCycles = [2,3,2];
}
def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
let Latency = 6;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,3,2];
+ let ResourceCycles = [2,3,2];
}
def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>;
def ICXWriteResGroup47 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort78,ICXPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
def ICXWriteResGroup48 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>;
def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
"VCVTPD2UQQ(Z128|Z256)rr",
@@ -985,7 +985,7 @@ def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr,
VCVTPD2UQQZrr,
@@ -999,7 +999,7 @@ def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr,
def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
"VEXPANDPS(Z|Z128|Z256)rr",
@@ -1025,7 +1025,7 @@ def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
def ICXWriteResGroup54 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
"IST_F(16|32)m",
@@ -1034,28 +1034,28 @@ def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>;
def ICXWriteResGroup56 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>;
def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort01]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
"MMX_CVT(T?)PS2PIrr",
@@ -1086,21 +1086,21 @@ def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>;
def ICXWriteResGroup65 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort01]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
"VCVTPS2PHZ256mr(b?)",
@@ -1109,7 +1109,7 @@ def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
def ICXWriteResGroup66 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
"VPMOVDW(Z|Z128|Z256)mr(b?)",
@@ -1132,21 +1132,21 @@ def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>;
def ICXWriteResGroup69 : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort0156]> {
let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,4];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>;
def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm,
VPBROADCASTDrm,
@@ -1161,7 +1161,7 @@ def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm,
def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
@@ -1173,7 +1173,7 @@ def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm,
MMX_PADDSWrm,
@@ -1199,7 +1199,7 @@ def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm,
def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>;
def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
@@ -1207,7 +1207,7 @@ def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm",
"MOVBE(16|32|64)rm")>;
@@ -1215,7 +1215,7 @@ def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm",
def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
@@ -1223,7 +1223,7 @@ def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
@@ -1231,7 +1231,7 @@ def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort01]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
"VCVTSI642SSZrr",
@@ -1240,14 +1240,14 @@ def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
def ICXWriteResGroup86 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -1256,7 +1256,7 @@ def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
def ICXWriteResGroup87 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
@@ -1264,14 +1264,14 @@ def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm",
def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,5];
+ let ResourceCycles = [1,5];
}
def: InstRW<[ICXWriteResGroup88], (instrs STD)>;
def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
@@ -1287,14 +1287,14 @@ def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)",
"VPBROADCAST(B|W)(Z128)?rm",
@@ -1307,7 +1307,7 @@ def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)",
def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort01]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
"VCVTPD2DQ(Y|Z256)rr",
@@ -1326,7 +1326,7 @@ def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
VCVTPD2DQZrr,
@@ -1345,7 +1345,7 @@ def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
VPBLENDDrmi)>;
@@ -1381,7 +1381,7 @@ def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd],
def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm,
MMX_PACKSSWBrm,
@@ -1390,7 +1390,7 @@ def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm,
def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr",
"VPERMI2W256rr",
@@ -1402,7 +1402,7 @@ def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr",
def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
@@ -1410,7 +1410,7 @@ def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64,
def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort01]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
"VCVT(T?)SS2USI64Zrr")>;
@@ -1418,28 +1418,28 @@ def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>;
def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>;
def ICXWriteResGroup106 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort78]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
"VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
@@ -1449,7 +1449,7 @@ def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
def ICXWriteResGroup107 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -1457,7 +1457,7 @@ def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
@@ -1465,14 +1465,14 @@ def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
def ICXWriteResGroup108 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
def ICXWriteResGroup109 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,1,1];
+ let ResourceCycles = [1,1,1,1,1];
}
def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>;
@@ -1480,7 +1480,7 @@ def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>;
def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,2,2,2];
+ let ResourceCycles = [1,2,2,2];
}
def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
VPSCATTERQQZ128mr,
@@ -1490,14 +1490,14 @@ def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,3,1,2];
+ let ResourceCycles = [1,3,1,2];
}
def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>;
def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 11;
- let ReleaseAtCycles = [1,4,4,2];
+ let ResourceCycles = [1,4,4,2];
}
def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
VPSCATTERQQZ256mr,
@@ -1507,7 +1507,7 @@ def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 19;
- let ReleaseAtCycles = [1,8,8,2];
+ let ResourceCycles = [1,8,8,2];
}
def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr,
VPSCATTERQQZmr,
@@ -1517,14 +1517,14 @@ def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr,
def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
let Latency = 7;
let NumMicroOps = 36;
- let ReleaseAtCycles = [1,16,1,16,2];
+ let ResourceCycles = [1,16,1,16,2];
}
def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm",
"PEXT(32|64)rm")>;
@@ -1532,7 +1532,7 @@ def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm",
def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
"VPBROADCASTB(Z|Z256)rm(b?)",
@@ -1550,7 +1550,7 @@ def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm,
def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
VPBLENDDYrmi)>;
@@ -1609,14 +1609,14 @@ def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd],
def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 8;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
"RCR(8|16|32|64)m(1|i)")>;
@@ -1624,7 +1624,7 @@ def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
def ICXWriteResGroup128 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,3];
+ let ResourceCycles = [1,1,1,3];
}
def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@@ -1635,14 +1635,14 @@ def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
def ICXWriteResGroup130 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,2,1];
}
def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>;
def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,2,1,2,2];
+ let ResourceCycles = [1,2,1,2,2];
}
def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
VPSCATTERQDZ256mr,
@@ -1652,7 +1652,7 @@ def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 12;
- let ReleaseAtCycles = [1,4,1,4,2];
+ let ResourceCycles = [1,4,1,4,2];
}
def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
VSCATTERDPSZ128mr)>;
@@ -1660,7 +1660,7 @@ def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 20;
- let ReleaseAtCycles = [1,8,1,8,2];
+ let ResourceCycles = [1,8,1,8,2];
}
def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
VSCATTERDPSZ256mr)>;
@@ -1668,21 +1668,21 @@ def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> {
let Latency = 8;
let NumMicroOps = 36;
- let ReleaseAtCycles = [1,16,1,16,2];
+ let ResourceCycles = [1,16,1,16,2];
}
def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm,
VPMOVSXDQYrm,
@@ -1708,7 +1708,7 @@ def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
"VCMP(SD|SS)Zrm",
@@ -1734,7 +1734,7 @@ def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort01]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
"(V?)CVTPS2PDrm")>;
@@ -1742,7 +1742,7 @@ def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm",
"(V?)PHSUBSWrm")>;
@@ -1750,7 +1750,7 @@ def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm",
def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm",
"LSL(16|32|64)rm")>;
@@ -1758,7 +1758,7 @@ def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm",
def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>;
def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
@@ -1773,7 +1773,7 @@ def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
"VCMPPS(Z|Z256)rm(b?)i",
@@ -1802,7 +1802,7 @@ def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort01]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
"VCVTDQ2PSZ128rm(b?)",
@@ -1835,7 +1835,7 @@ def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
"VEXPANDPSZ128rm(b?)",
@@ -1845,7 +1845,7 @@ def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> {
let Latency = 10;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm,
VPHSUBSWYrm)>;
@@ -1853,21 +1853,21 @@ def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm,
def ICXWriteResGroup157 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 10;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,3];
+ let ResourceCycles = [1,1,1,1,1,3];
}
def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort01]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm,
VCVTPS2PDYrm)>;
@@ -1890,7 +1890,7 @@ def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
"VEXPANDPD(Z|Z256)rm(b?)",
@@ -1901,14 +1901,14 @@ def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2DQrm,
CVTTPD2DQrm,
@@ -1918,14 +1918,14 @@ def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2DQrm,
def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
let Latency = 11;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,3,2];
+ let ResourceCycles = [2,3,2];
}
def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
"RCR(16|32|64)rCL")>;
@@ -1933,42 +1933,42 @@ def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,5,1,2];
+ let ResourceCycles = [1,5,1,2];
}
def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>;
def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,9];
+ let ResourceCycles = [2,9];
}
def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
def ICXWriteResGroup174z : SchedWriteRes<[ICXPort0]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>;
def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort01]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
"VCVT(T?)SS2USI64Zrm(b?)")>;
@@ -1976,7 +1976,7 @@ def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
"VCVT(T?)PS2UQQZrm(b?)")>;
@@ -1984,7 +1984,7 @@ def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
"VPERMWZ256rm(b?)",
@@ -1993,14 +1993,14 @@ def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
let Latency = 13;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
"VPERMT2W128rm(b?)")>;
@@ -2008,14 +2008,14 @@ def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
"VCVTPD2UDQZrm(b?)",
@@ -2027,7 +2027,7 @@ def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
let Latency = 14;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
"VPERMI2Wrm(b?)",
@@ -2037,98 +2037,98 @@ def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
- let ReleaseAtCycles = [2,4,1,3];
+ let ResourceCycles = [2,4,1,3];
}
def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>;
def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> {
let Latency = 15;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
let Latency = 15;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,2,2,1,2];
+ let ResourceCycles = [1,2,2,1,2];
}
def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 15;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,1,1,5,1,1];
+ let ResourceCycles = [1,1,1,5,1,1];
}
def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
def ICXWriteResGroup199 : SchedWriteRes<[ICXPort49,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,1,1,4,2,5];
+ let ResourceCycles = [1,1,1,4,2,5];
}
def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>;
def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> {
let Latency = 12;
let NumMicroOps = 34;
- let ReleaseAtCycles = [1, 4, 5];
+ let ResourceCycles = [1, 4, 5];
}
def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>;
def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> {
let Latency = 17;
let NumMicroOps = 15;
- let ReleaseAtCycles = [2,1,2,4,2,4];
+ let ResourceCycles = [2,1,2,4,2,4];
}
def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>;
def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> {
let Latency = 21;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,5];
+ let ResourceCycles = [1,1,1,5];
}
def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>;
def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort78,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 18;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,1,1,4,1,2];
+ let ResourceCycles = [2,1,1,4,1,2];
}
def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> {
let Latency = 22;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort0]> {
let Latency = 22;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> {
let Latency = 20;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
let Latency = 17;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
VGATHERDPDZ128rm, VPGATHERDQZ128rm,
@@ -2137,7 +2137,7 @@ def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
let Latency = 19;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,4,1,1];
+ let ResourceCycles = [1,4,1,1];
}
def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
VGATHERQPDZ256rm, VPGATHERQQZ256rm,
@@ -2147,7 +2147,7 @@ def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
let Latency = 21;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,8,1,1];
+ let ResourceCycles = [1,8,1,1];
}
def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
VGATHERDPDZrm, VPGATHERDQZrm,
@@ -2157,35 +2157,35 @@ def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> {
let Latency = 25;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,16,1,1];
+ let ResourceCycles = [1,16,1,1];
}
def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
def ICXWriteResGroup219 : SchedWriteRes<[ICXPort49,ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 20;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,1,2];
+ let ResourceCycles = [1,1,1,1,1,1,2];
}
def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>;
def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> {
let Latency = 20;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,2,7];
+ let ResourceCycles = [1,2,7];
}
def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>;
def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let Latency = 22;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
let Latency = 18;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
VGATHERQPDrm, VPGATHERQQrm,
@@ -2194,7 +2194,7 @@ def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
let Latency = 20;
let NumMicroOps = 5; // 2 uops peform multiple loads
- let ReleaseAtCycles = [1,4,1,1];
+ let ResourceCycles = [1,4,1,1];
}
def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
VGATHERDPSrm, VPGATHERDDrm,
@@ -2204,14 +2204,14 @@ def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> {
let Latency = 22;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,8,1,1];
+ let ResourceCycles = [1,8,1,1];
}
def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
let Latency = 22;
let NumMicroOps = 14;
- let ReleaseAtCycles = [5,5,4];
+ let ResourceCycles = [5,5,4];
}
def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
"VPCONFLICTQZ256rr")>;
@@ -2219,42 +2219,42 @@ def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
- let ReleaseAtCycles = [2,1,4,1,1,4,6];
+ let ResourceCycles = [2,1,4,1,1,4,6];
}
def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>;
def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 25;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let Latency = 27;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
let Latency = 29;
let NumMicroOps = 15;
- let ReleaseAtCycles = [5,5,1,4];
+ let ResourceCycles = [5,5,1,4];
}
def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> {
let Latency = 30;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,3,4,10];
+ let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri",
"IN(8|16|32)rr")>;
@@ -2262,7 +2262,7 @@ def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri",
def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,2,1,4,10];
+ let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
@@ -2270,7 +2270,7 @@ def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir",
def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
let Latency = 37;
let NumMicroOps = 21;
- let ReleaseAtCycles = [9,7,5];
+ let ResourceCycles = [9,7,5];
}
def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
"VPCONFLICTQZrr")>;
@@ -2278,35 +2278,35 @@ def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> {
let Latency = 37;
let NumMicroOps = 31;
- let ReleaseAtCycles = [1,8,1,21];
+ let ResourceCycles = [1,8,1,21];
}
def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>;
def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort49,ICXPort5,ICXPort6,ICXPort23,ICXPort78,ICXPort15,ICXPort0156]> {
let Latency = 40;
let NumMicroOps = 18;
- let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
+ let ResourceCycles = [1,1,2,3,1,1,1,8];
}
def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>;
def ICXWriteResGroup253 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
let Latency = 41;
let NumMicroOps = 39;
- let ReleaseAtCycles = [1,10,1,1,26];
+ let ResourceCycles = [1,10,1,1,26];
}
def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>;
def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> {
let Latency = 42;
let NumMicroOps = 22;
- let ReleaseAtCycles = [2,20];
+ let ResourceCycles = [2,20];
}
def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>;
def ICXWriteResGroup255 : SchedWriteRes<[ICXPort49,ICXPort6,ICXPort23,ICXPort78,ICXPort0156]> {
let Latency = 42;
let NumMicroOps = 40;
- let ReleaseAtCycles = [1,11,1,1,26];
+ let ResourceCycles = [1,11,1,1,26];
}
def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>;
def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
@@ -2314,7 +2314,7 @@ def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
let Latency = 44;
let NumMicroOps = 22;
- let ReleaseAtCycles = [9,7,1,5];
+ let ResourceCycles = [9,7,1,5];
}
def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
"VPCONFLICTQZrm(b?)")>;
@@ -2322,56 +2322,56 @@ def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> {
let Latency = 62;
let NumMicroOps = 64;
- let ReleaseAtCycles = [2,8,5,10,39];
+ let ResourceCycles = [2,8,5,10,39];
}
def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>;
def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 63;
let NumMicroOps = 88;
- let ReleaseAtCycles = [4,4,31,1,2,1,45];
+ let ResourceCycles = [4,4,31,1,2,1,45];
}
def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>;
def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> {
let Latency = 63;
let NumMicroOps = 90;
- let ReleaseAtCycles = [4,2,33,1,2,1,47];
+ let ResourceCycles = [4,2,33,1,2,1,47];
}
def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>;
def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> {
let Latency = 67;
let NumMicroOps = 35;
- let ReleaseAtCycles = [17,11,7];
+ let ResourceCycles = [17,11,7];
}
def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> {
let Latency = 74;
let NumMicroOps = 36;
- let ReleaseAtCycles = [17,11,1,7];
+ let ResourceCycles = [17,11,1,7];
}
def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
- let ReleaseAtCycles = [6,3,6];
+ let ResourceCycles = [6,3,6];
}
def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>;
def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort49,ICXPort5,ICXPort6,ICXPort78,ICXPort06,ICXPort0156]> {
let Latency = 106;
let NumMicroOps = 100;
- let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
+ let ResourceCycles = [9,1,11,16,1,11,21,30];
}
def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>;
def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
let Latency = 140;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>;
@@ -2458,7 +2458,7 @@ def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
def ICXWritePSUB : SchedWriteRes<[ICXPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[
@@ -2481,7 +2481,7 @@ def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -2495,13 +2495,13 @@ def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
// CMOVs that use both Z and C flag require an extra uop.
def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> {
let Latency = 7;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
let NumMicroOps = 3;
}
@@ -2521,13 +2521,13 @@ def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort49,ICXPort78,ICXPort06]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index f0b98a64cfdda7..8c01119ed9b8c0 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -90,7 +90,7 @@ multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -98,7 +98,7 @@ multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -486,44 +486,44 @@ defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1
def : WriteRes<WritePCmpIStrM, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [SBPort015]> {
let Latency = 11;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
let Latency = 17;
- let ReleaseAtCycles = [7, 1];
+ let ResourceCycles = [7, 1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [SBPort015]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
let Latency = 10;
- let ReleaseAtCycles = [7, 1];
+ let ResourceCycles = [7, 1];
}
// MOVMSK Instructions.
@@ -536,48 +536,48 @@ def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; }
def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def : WriteRes<WriteAESIMC, [SBPort5]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
let Latency = 18;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [SBPort015]> {
let Latency = 8;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
let Latency = 14;
- let ReleaseAtCycles = [10, 1];
+ let ResourceCycles = [10, 1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SBPort015]> {
let Latency = 14;
- let ReleaseAtCycles = [18];
+ let ResourceCycles = [18];
}
def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
let Latency = 20;
- let ReleaseAtCycles = [17, 1];
+ let ResourceCycles = [17, 1];
}
// Load/store MXCSR.
// FIXME: This is probably wrong. Only STMXCSR should require Port4.
-def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
@@ -601,7 +601,7 @@ defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1
def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
COM_FST0r,
@@ -611,7 +611,7 @@ def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
LD_Frr, ST_Frr, ST_FPrr)>;
@@ -620,14 +620,14 @@ def: InstRW<[SBWriteResGroup2], (instrs RET64)>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
MMX_PABSDrr,
@@ -641,7 +641,7 @@ def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroup11], (instrs SCASB,
SCASL,
@@ -651,14 +651,14 @@ def: InstRW<[SBWriteResGroup11], (instrs SCASB,
def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>;
def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup15], (instrs CWD,
FNSTSW16r)>;
@@ -666,7 +666,7 @@ def: InstRW<[SBWriteResGroup15], (instrs CWD,
def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
MMX_MOVDQ2Qrr)>;
@@ -674,21 +674,21 @@ def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>;
def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
let Latency = 3;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
def SBWriteResGroup23 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -696,63 +696,63 @@ def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def SBWriteResGroup24 : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
let Latency = 3;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,4,2];
+ let ResourceCycles = [1,1,4,2];
}
def: InstRW<[SBWriteResGroup24], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def SBWriteResGroup24b : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
let Latency = 4;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,4,2];
+ let ResourceCycles = [1,1,4,2];
}
def: InstRW<[SBWriteResGroup24b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>;
def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
def SBWriteResGroup30 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
let Latency = 3;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,3,4];
+ let ResourceCycles = [1,3,4];
}
def: InstRW<[SBWriteResGroup30], (instrs LOOP)>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort1,SBPort5,SBPort015,SBPort05]> {
let Latency = 4;
let NumMicroOps = 12;
- let ReleaseAtCycles = [1,3,6,2];
+ let ResourceCycles = [1,3,6,2];
}
def: InstRW<[SBWriteResGroup31], (instrs LOOPE, LOOPNE)>;
def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> {
let Latency = 5;
let NumMicroOps = 8;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
"RCR(8|16|32|64)rCL")>;
@@ -760,21 +760,21 @@ def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup35], (instrs CLI)>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>;
def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
@@ -782,7 +782,7 @@ def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
@@ -791,21 +791,21 @@ def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>;
def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
"PUSHF(16|64)")>;
@@ -813,21 +813,21 @@ def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup48], (instrs VBROADCASTSSrm)>;
def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
@@ -843,14 +843,14 @@ def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
MMX_PABSDrm,
@@ -863,14 +863,14 @@ def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>;
def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
"ST_FP(32|64|80)m")>;
@@ -878,7 +878,7 @@ def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
VBROADCASTSSYrm,
@@ -889,49 +889,49 @@ def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>;
def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQrm)>;
def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>;
def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>;
def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup64], (instrs FARJMP64m)>;
def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>;
def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
"STR(16|32|64)r")>;
@@ -939,7 +939,7 @@ def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>;
def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
@@ -947,7 +947,7 @@ def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -956,21 +956,21 @@ def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 8;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
}
def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2,3];
+ let ResourceCycles = [2,3];
}
def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
CMPSL,
@@ -980,14 +980,14 @@ def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,2];
+ let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;
def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,2];
+ let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -995,7 +995,7 @@ def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,2];
+ let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
@@ -1003,21 +1003,21 @@ def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SBWriteResGroup87], (instrs FARCALL64m)>;
def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
let Latency = 9;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
"IST_FP(16|32|64)m")>;
@@ -1025,7 +1025,7 @@ def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 9;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,2,3];
+ let ResourceCycles = [1,2,3];
}
def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@@ -1036,14 +1036,14 @@ def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,3];
+ let ResourceCycles = [1,2,3];
}
def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,2,1];
+ let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
@@ -1051,14 +1051,14 @@ def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr,
def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,2,1,1];
+ let ResourceCycles = [1,1,2,1,1];
}
def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
@@ -1066,21 +1066,21 @@ def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [7,4];
+ let ResourceCycles = [7,4];
}
def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
"RCR(8|16|32|64)m")>;
@@ -1088,49 +1088,49 @@ def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>;
def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 31;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 34;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> {
let Latency = 9;
let NumMicroOps = 20;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>;
def SBWriteResGroupVzeroupper : SchedWriteRes<[]> {
let Latency = 1;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>;
@@ -1190,7 +1190,7 @@ def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -1202,13 +1202,13 @@ def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>;
// CMOVs that use both Z and C flag require an extra uop.
def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
let NumMicroOps = 3;
}
def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let Latency = 8;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
let NumMicroOps = 4;
}
@@ -1228,13 +1228,13 @@ def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
index 6a426ef4cf5433..bcf1601f26bb2d 100644
--- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td
+++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
@@ -102,7 +102,7 @@ multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -110,7 +110,7 @@ multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SPRPort02_03_11], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -305,7 +305,7 @@ defm : SPRWriteResPair<WriteFSqrt64Y, [SPRPort00], 18, [1], 1, 3>;
// Warning: negtive load latency.
defm : SPRWriteResPair<WriteFSqrt64Z, [SPRPort00, SPRPort00_05], 32, [2, 1], 3, -1>;
def : WriteRes<WriteFSqrt80, [SPRPortInvalid, SPRPort00]> {
- let ReleaseAtCycles = [7, 1];
+ let ResourceCycles = [7, 1];
let Latency = 21;
}
defm : SPRWriteResPair<WriteFSqrtX, [SPRPort00], 12, [1], 1, 7>;
@@ -524,7 +524,7 @@ def : InstRW<[SPRWriteResGroup0], (instregex "^AA(D|N)D64mr$",
"^A(X?)OR64mr$")>;
def SPRWriteResGroup1 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 6;
}
@@ -545,7 +545,7 @@ def SPRWriteResGroup3 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRP
def : InstRW<[SPRWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
def SPRWriteResGroup4 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
@@ -642,7 +642,7 @@ def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S
def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instrs VPERMBZ128rm)>;
def SPRWriteResGroup11 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
@@ -730,7 +730,7 @@ def SPRWriteResGroup16 : SchedWriteRes<[SPRPort01_05_10]> {
def : InstRW<[SPRWriteResGroup16], (instregex "^ANDN(32|64)rr$")>;
def SPRWriteResGroup17 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [5, 2, 1, 1];
+ let ResourceCycles = [5, 2, 1, 1];
let Latency = 10;
let NumMicroOps = 9;
}
@@ -743,7 +743,7 @@ def : InstRW<[SPRWriteResGroup18], (instregex "^BT((C|R|S)?)64rr$",
"^P(DEP|EXT)(32|64)rr$")>;
def SPRWriteResGroup19 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 10;
}
@@ -809,14 +809,14 @@ def SPRWriteResGroup28 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPR
def : InstRW<[SPRWriteResGroup28], (instrs CLFLUSHOPT)>;
def SPRWriteResGroup29 : SchedWriteRes<[SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup29], (instrs CLI)>;
def SPRWriteResGroup30 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort05]> {
- let ReleaseAtCycles = [6, 1, 3];
+ let ResourceCycles = [6, 1, 3];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 10;
}
@@ -830,35 +830,35 @@ def : InstRW<[SPRWriteResGroup31], (instregex "^MOV16o(16|32|64)a$")>;
def : InstRW<[SPRWriteResGroup31], (instrs CLWB)>;
def SPRWriteResGroup32 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
- let ReleaseAtCycles = [5, 2];
+ let ResourceCycles = [5, 2];
let Latency = 6;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup32], (instregex "^CMPS(B|L|Q|W)$")>;
def SPRWriteResGroup33 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+ let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
let Latency = 32;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup33], (instrs CMPXCHG16B)>;
def SPRWriteResGroup34 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
+ let ResourceCycles = [4, 7, 2, 1, 1, 1];
let Latency = 25;
let NumMicroOps = 16;
}
def : InstRW<[SPRWriteResGroup34], (instrs CMPXCHG8B)>;
def SPRWriteResGroup35 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 1, 1, 1];
+ let ResourceCycles = [1, 2, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup35], (instrs CMPXCHG8rm)>;
def SPRWriteResGroup36 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
+ let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
let Latency = 18;
let NumMicroOps = 26;
}
@@ -901,7 +901,7 @@ def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CV
def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instrs VCVTSI2SSrr)>;
def SPRWriteResGroup40 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 8;
let NumMicroOps = 3;
}
@@ -994,7 +994,7 @@ def : InstRW<[SPRWriteResGroup52], (instregex "^ENQCMD(S?)(16|32|64)$",
def : InstRW<[SPRWriteResGroup52], (instrs PUSHF32)>;
def SPRWriteResGroup53 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
+ let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
let Latency = 126;
let NumMicroOps = 57;
}
@@ -1040,14 +1040,14 @@ def : InstRW<[SPRWriteResGroup58], (instrs FBSTPm,
VMPTRSTm)>;
def SPRWriteResGroup59 : SchedWriteRes<[SPRPort00_05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup59], (instrs FDECSTP)>;
def SPRWriteResGroup60 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 11;
let NumMicroOps = 3;
}
@@ -1071,21 +1071,21 @@ def SPRWriteResGroup62 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11
def : InstRW<[SPRWriteResGroup62], (instrs FLDCW16m)>;
def SPRWriteResGroup63 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 5, 10, 39, 8];
+ let ResourceCycles = [2, 5, 10, 39, 8];
let Latency = 62;
let NumMicroOps = 64;
}
def : InstRW<[SPRWriteResGroup63], (instrs FLDENVm)>;
def SPRWriteResGroup64 : SchedWriteRes<[SPRPort00_01_05_06]> {
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let Latency = 4;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup64], (instrs FNCLEX)>;
def SPRWriteResGroup65 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [6, 3, 6];
+ let ResourceCycles = [6, 3, 6];
let Latency = 75;
let NumMicroOps = 15;
}
@@ -1110,28 +1110,28 @@ def SPRWriteResGroup68 : SchedWriteRes<[SPRPort00, SPRPort04, SPRPort04_09]> {
def : InstRW<[SPRWriteResGroup68], (instrs FNSTSWm)>;
def SPRWriteResGroup69 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_06, SPRPort01, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
- let ReleaseAtCycles = [9, 11, 21, 1, 30, 11, 16, 1];
+ let ResourceCycles = [9, 11, 21, 1, 30, 11, 16, 1];
let Latency = 106;
let NumMicroOps = 100;
}
def : InstRW<[SPRWriteResGroup69], (instrs FSTENVm)>;
def SPRWriteResGroup70 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
- let ReleaseAtCycles = [4, 1, 2, 1, 47, 33, 2];
+ let ResourceCycles = [4, 1, 2, 1, 47, 33, 2];
let Latency = 63;
let NumMicroOps = 90;
}
def : InstRW<[SPRWriteResGroup70], (instrs FXRSTOR)>;
def SPRWriteResGroup71 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
- let ReleaseAtCycles = [4, 1, 2, 1, 45, 31, 4];
+ let ResourceCycles = [4, 1, 2, 1, 45, 31, 4];
let Latency = 63;
let NumMicroOps = 88;
}
def : InstRW<[SPRWriteResGroup71], (instrs FXRSTOR64)>;
def SPRWriteResGroup72 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+ let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 110;
}
@@ -1208,41 +1208,41 @@ def : InstRW<[SPRWriteResGroup74], (instrs VCVTSH2SSZrr,
VGF2P8MULBYrr)>;
def SPRWriteResGroup75 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
+ let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[SPRWriteResGroup75], (instrs IN16ri)>;
def SPRWriteResGroup76 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
+ let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[SPRWriteResGroup76], (instrs IN16rr)>;
def SPRWriteResGroup77 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
+ let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
let Latency = 35;
let NumMicroOps = 94;
}
def : InstRW<[SPRWriteResGroup77], (instrs IN32ri)>;
def SPRWriteResGroup78 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
+ let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
let NumMicroOps = 99;
}
def : InstRW<[SPRWriteResGroup78], (instrs IN32rr)>;
def SPRWriteResGroup79 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
+ let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
let Latency = 35;
let NumMicroOps = 87;
}
def : InstRW<[SPRWriteResGroup79], (instrs IN8ri)>;
def SPRWriteResGroup80 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
+ let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
let Latency = 35;
let NumMicroOps = 86;
}
@@ -1265,28 +1265,28 @@ def : InstRW<[SPRWriteResGroup82], (instrs INC32r_alt,
VBROADCASTI32X2Z128rm)>;
def SPRWriteResGroup83 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
+ let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 83;
}
def : InstRW<[SPRWriteResGroup83], (instrs INSB)>;
def SPRWriteResGroup84 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
+ let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
let Latency = 20;
let NumMicroOps = 92;
}
def : InstRW<[SPRWriteResGroup84], (instrs INSL)>;
def SPRWriteResGroup85 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
+ let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 86;
}
def : InstRW<[SPRWriteResGroup85], (instrs INSW)>;
def SPRWriteResGroup86 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
+ let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 42;
}
@@ -1393,35 +1393,35 @@ def : InstRW<[SPRWriteResGroup96], (instregex "^K((OR)?)TEST(B|D|Q|W)rr$",
def : InstRW<[SPRWriteResGroup96], (instrs VMOVSDto64Zrr)>;
def SPRWriteResGroup97 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [8, 2, 14, 3, 1];
+ let ResourceCycles = [8, 2, 14, 3, 1];
let Latency = 198;
let NumMicroOps = 81;
}
def : InstRW<[SPRWriteResGroup97], (instrs LAR16rm)>;
def SPRWriteResGroup98 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 66;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup98], (instrs LAR16rr)>;
def SPRWriteResGroup99 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 85;
}
def : InstRW<[SPRWriteResGroup99], (instrs LAR32rm)>;
def SPRWriteResGroup100 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 65;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
def SPRWriteResGroup101 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 87;
}
@@ -1434,7 +1434,7 @@ def SPRWriteResGroup102 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
def : InstRW<[SPRWriteResGroup102], (instrs LEA16r)>;
def SPRWriteResGroup103 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 6;
let NumMicroOps = 4;
}
@@ -1443,77 +1443,77 @@ def : InstRW<[SPRWriteResGroup103], (instregex "^LODS(B|W)$",
def : InstRW<[SPRWriteResGroup103], (instrs LEAVE)>;
def SPRWriteResGroup104 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup104], (instrs LEAVE64)>;
def SPRWriteResGroup105 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
+ let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 14;
}
def : InstRW<[SPRWriteResGroup105], (instrs LGDT64m)>;
def SPRWriteResGroup106 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
+ let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 14;
}
def : InstRW<[SPRWriteResGroup106], (instrs LIDT64m)>;
def SPRWriteResGroup107 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [5, 3, 2, 1, 1];
+ let ResourceCycles = [5, 3, 2, 1, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 12;
}
def : InstRW<[SPRWriteResGroup107], (instrs LLDT16m)>;
def SPRWriteResGroup108 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
+ let ResourceCycles = [1, 4, 3, 1, 1, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 11;
}
def : InstRW<[SPRWriteResGroup108], (instrs LLDT16r)>;
def SPRWriteResGroup109 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
+ let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 27;
}
def : InstRW<[SPRWriteResGroup109], (instrs LMSW16m)>;
def SPRWriteResGroup110 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
+ let ResourceCycles = [5, 7, 1, 2, 5, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup110], (instrs LMSW16r)>;
def SPRWriteResGroup111 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 5;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup111], (instregex "^LODS(L|Q)$")>;
def SPRWriteResGroup112 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [2, 4, 1];
+ let ResourceCycles = [2, 4, 1];
let Latency = 3;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup112], (instrs LOOP)>;
def SPRWriteResGroup113 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [4, 6, 1];
+ let ResourceCycles = [4, 6, 1];
let Latency = 3;
let NumMicroOps = 11;
}
def : InstRW<[SPRWriteResGroup113], (instrs LOOPE)>;
def SPRWriteResGroup114 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [4, 6, 1];
+ let ResourceCycles = [4, 6, 1];
let Latency = 2;
let NumMicroOps = 11;
}
@@ -1526,14 +1526,14 @@ def SPRWriteResGroup115 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort0
def : InstRW<[SPRWriteResGroup115], (instrs LRET64)>;
def SPRWriteResGroup116 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 5, 3, 3, 1];
+ let ResourceCycles = [1, 5, 3, 3, 1];
let Latency = 70;
let NumMicroOps = 13;
}
def : InstRW<[SPRWriteResGroup116], (instregex "^LSL(16|32|64)rm$")>;
def SPRWriteResGroup117 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
+ let ResourceCycles = [1, 4, 4, 3, 2, 1];
let Latency = 63;
let NumMicroOps = 15;
}
@@ -1582,7 +1582,7 @@ def SPRWriteResGroup123 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
def : InstRW<[SPRWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
def SPRWriteResGroup124 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 12;
let NumMicroOps = 4;
}
@@ -1627,7 +1627,7 @@ def SPRWriteResGroup128 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
def SPRWriteResGroup129 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 12;
let NumMicroOps = 3;
}
@@ -1635,7 +1635,7 @@ def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|W
def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
def SPRWriteResGroup130 : SchedWriteRes<[SPRPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
@@ -1671,14 +1671,14 @@ def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(3
"^VPTERNLOG(D|Q)Zrmi((kz)?)$")>;
def SPRWriteResGroup132 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 11;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
def SPRWriteResGroup133 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 3;
let NumMicroOps = 3;
}
@@ -1747,7 +1747,7 @@ def SPRWriteResGroup142 : SchedWriteRes<[SPRPort02_03_11]> {
def : InstRW<[SPRWriteResGroup142], (instrs MOV64ao32)>;
def SPRWriteResGroup143 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
+ let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
let Latency = 217;
let NumMicroOps = 48;
}
@@ -1766,7 +1766,7 @@ def SPRWriteResGroup145 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SP
def : InstRW<[SPRWriteResGroup145], (instrs MOV64rc)>;
def SPRWriteResGroup146 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
- let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
+ let ResourceCycles = [3, 4, 8, 4, 2, 3];
let Latency = 181;
let NumMicroOps = 24;
}
@@ -1851,7 +1851,7 @@ def SPRWriteResGroup158 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
def : InstRW<[SPRWriteResGroup158], (instrs MOVNTImr)>;
def SPRWriteResGroup159 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [4, 1, 1, 1];
+ let ResourceCycles = [4, 1, 1, 1];
let Latency = 8;
let NumMicroOps = 7;
}
@@ -1872,7 +1872,7 @@ def : InstRW<[SPRWriteResGroup160], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
def : InstRW<[SPRWriteResGroup160], (instrs VPBLENDDrri)>;
def SPRWriteResGroup161 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [4, 1, 1, 1];
+ let ResourceCycles = [4, 1, 1, 1];
let Latency = 7;
let NumMicroOps = 7;
}
@@ -1934,70 +1934,70 @@ def : InstRW<[SPRWriteResGroup167], (instregex "^MUL_F(P?)rST0$",
def : InstRW<[SPRWriteResGroup167], (instrs MUL_FST0r)>;
def SPRWriteResGroup168 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort05, SPRPort06]> {
- let ReleaseAtCycles = [7, 1, 2];
+ let ResourceCycles = [7, 1, 2];
let Latency = 20;
let NumMicroOps = 10;
}
def : InstRW<[SPRWriteResGroup168], (instrs MWAITrr)>;
def SPRWriteResGroup169 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
+ let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
def : InstRW<[SPRWriteResGroup169], (instrs OUT16ir)>;
def SPRWriteResGroup170 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
+ let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
def : InstRW<[SPRWriteResGroup170], (instrs OUT16rr)>;
def SPRWriteResGroup171 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
+ let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
def : InstRW<[SPRWriteResGroup171], (instrs OUT32ir)>;
def SPRWriteResGroup172 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
+ let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
def : InstRW<[SPRWriteResGroup172], (instrs OUT32rr)>;
def SPRWriteResGroup173 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
+ let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
def : InstRW<[SPRWriteResGroup173], (instrs OUT8ir)>;
def SPRWriteResGroup174 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
+ let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
def : InstRW<[SPRWriteResGroup174], (instrs OUT8rr)>;
def SPRWriteResGroup175 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
+ let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 80;
}
def : InstRW<[SPRWriteResGroup175], (instrs OUTSB)>;
def SPRWriteResGroup176 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
+ let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 89;
}
def : InstRW<[SPRWriteResGroup176], (instrs OUTSL)>;
def SPRWriteResGroup177 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
+ let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 83;
}
@@ -2055,14 +2055,14 @@ def : InstRW<[SPRWriteResGroup182], (instregex "^(V?)PEXTR(D|Q)mr$",
"^VPMOVQDZ128mr(k?)$")>;
def SPRWriteResGroup183 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 9;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
def SPRWriteResGroup184 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 2;
let NumMicroOps = 3;
}
@@ -2077,14 +2077,14 @@ def : InstRW<[SPRWriteResGroup185], (instregex "^POP(16|32|64)rmm$",
"^PUSH(16|32)rmm$")>;
def SPRWriteResGroup186 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [6, 2, 1, 1];
+ let ResourceCycles = [6, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 10;
}
def : InstRW<[SPRWriteResGroup186], (instrs POPF16)>;
def SPRWriteResGroup187 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
@@ -2097,21 +2097,21 @@ def : InstRW<[SPRWriteResGroup188], (instregex "^PREFETCHT(0|1|2)$")>;
def : InstRW<[SPRWriteResGroup188], (instrs PREFETCHNTA)>;
def SPRWriteResGroup189 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort06]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup189], (instregex "^PTWRITE((64)?)m$")>;
def SPRWriteResGroup190 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup190], (instrs PTWRITE64r)>;
def SPRWriteResGroup191 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 4;
}
@@ -2139,49 +2139,49 @@ def SPRWriteResGroup195 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]>
def : InstRW<[SPRWriteResGroup195], (instregex "^PUSH(F|G)S64$")>;
def SPRWriteResGroup196 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [2, 3, 2];
+ let ResourceCycles = [2, 3, 2];
let Latency = 8;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup196], (instregex "^RC(L|R)(16|32|64)rCL$")>;
def SPRWriteResGroup197 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup197, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
def SPRWriteResGroup198 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [1, 5, 2];
+ let ResourceCycles = [1, 5, 2];
let Latency = 20;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup198, WriteRMW], (instrs RCL8mCL)>;
def SPRWriteResGroup199 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [2, 5, 2];
+ let ResourceCycles = [2, 5, 2];
let Latency = 7;
let NumMicroOps = 9;
}
def : InstRW<[SPRWriteResGroup199], (instrs RCL8rCL)>;
def SPRWriteResGroup200 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [2, 4, 3];
+ let ResourceCycles = [2, 4, 3];
let Latency = 20;
let NumMicroOps = 9;
}
def : InstRW<[SPRWriteResGroup200, WriteRMW], (instrs RCR8mCL)>;
def SPRWriteResGroup201 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [3, 4, 3];
+ let ResourceCycles = [3, 4, 3];
let Latency = 9;
let NumMicroOps = 10;
}
def : InstRW<[SPRWriteResGroup201], (instrs RCR8rCL)>;
def SPRWriteResGroup202 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort01_05_10, SPRPort05]> {
- let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
+ let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 54;
}
@@ -2199,49 +2199,49 @@ def SPRWriteResGroup204 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SP
def : InstRW<[SPRWriteResGroup204], (instrs RDPKRUr)>;
def SPRWriteResGroup205 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
- let ReleaseAtCycles = [9, 6, 2, 1];
+ let ResourceCycles = [9, 6, 2, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 18;
}
def : InstRW<[SPRWriteResGroup205], (instrs RDPMC)>;
def SPRWriteResGroup206 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = 1386;
let NumMicroOps = 25;
}
def : InstRW<[SPRWriteResGroup206], (instrs RDRAND16r)>;
def SPRWriteResGroup207 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 25;
}
def : InstRW<[SPRWriteResGroup207], (instregex "^RDRAND(32|64)r$")>;
def SPRWriteResGroup208 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = 1381;
let NumMicroOps = 25;
}
def : InstRW<[SPRWriteResGroup208], (instrs RDSEED16r)>;
def SPRWriteResGroup209 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 25;
}
def : InstRW<[SPRWriteResGroup209], (instregex "^RDSEED(32|64)r$")>;
def SPRWriteResGroup210 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
- let ReleaseAtCycles = [5, 6, 3, 1];
+ let ResourceCycles = [5, 6, 3, 1];
let Latency = 18;
let NumMicroOps = 15;
}
def : InstRW<[SPRWriteResGroup210], (instrs RDTSC)>;
def SPRWriteResGroup211 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
+ let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
let Latency = 42;
let NumMicroOps = 21;
}
@@ -2254,7 +2254,7 @@ def SPRWriteResGroup212 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
def : InstRW<[SPRWriteResGroup212], (instrs RET64)>;
def SPRWriteResGroup213 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
@@ -2264,20 +2264,20 @@ def SPRWriteResGroup214 : SchedWriteRes<[]>;
def : InstRW<[SPRWriteResGroup214], (instrs REX64_PREFIX)>;
def SPRWriteResGroup215 : SchedWriteRes<[SPRPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup215, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
def SPRWriteResGroup216 : SchedWriteRes<[SPRPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup216], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
def SPRWriteResGroup217 : SchedWriteRes<[SPRPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
@@ -2286,7 +2286,7 @@ def : InstRW<[SPRWriteResGroup217, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
"^(RO|SA|SH)R8mCL$")>;
def SPRWriteResGroup218 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 15;
let NumMicroOps = 3;
}
@@ -2299,7 +2299,7 @@ def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S
"^VRNDSCALES(D|S)Zm_Int((k|kz)?)$")>;
def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 8;
let NumMicroOps = 2;
}
@@ -2312,7 +2312,7 @@ def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)r$",
"^VROUNDP(D|S)Yr$")>;
def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
@@ -2338,7 +2338,7 @@ def : InstRW<[SPRWriteResGroup223], (instregex "^S(A|H)RX(32|64)rr$",
"^SHLX(32|64)rr$")>;
def SPRWriteResGroup224 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 2, 1, 1, 1];
+ let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 7;
}
@@ -2351,7 +2351,7 @@ def SPRWriteResGroup225 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
def : InstRW<[SPRWriteResGroup225], (instrs SFENCE)>;
def SPRWriteResGroup226 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 2, 2];
+ let ResourceCycles = [1, 2, 2, 2];
let Latency = 21;
let NumMicroOps = 7;
}
@@ -2370,14 +2370,14 @@ def SPRWriteResGroup228 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
def : InstRW<[SPRWriteResGroup228], (instrs SHA1MSG1rr)>;
def SPRWriteResGroup229 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 2, 1, 2, 1];
+ let ResourceCycles = [2, 2, 1, 2, 1];
let Latency = 13;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup229, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
def SPRWriteResGroup230 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05]> {
- let ReleaseAtCycles = [2, 2, 1, 2];
+ let ResourceCycles = [2, 2, 1, 2];
let Latency = 6;
let NumMicroOps = 7;
}
@@ -2428,21 +2428,21 @@ def : InstRW<[SPRWriteResGroup234], (instrs SHA1RNDS4rri,
SHA256RNDS2rr)>;
def SPRWriteResGroup235 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [3, 2, 1, 1, 1];
+ let ResourceCycles = [3, 2, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup235, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
def SPRWriteResGroup236 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [3, 2, 1, 1];
+ let ResourceCycles = [3, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup236], (instrs SHA256MSG1rr)>;
def SPRWriteResGroup237 : SchedWriteRes<[SPRPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 6;
let NumMicroOps = 2;
}
@@ -2489,21 +2489,21 @@ def SPRWriteResGroup243 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
def : InstRW<[SPRWriteResGroup243], (instrs STD)>;
def SPRWriteResGroup244 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [1, 4, 1];
+ let ResourceCycles = [1, 4, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup244], (instrs STI)>;
def SPRWriteResGroup245 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 8;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup245], (instrs STOSB)>;
def SPRWriteResGroup246 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 7;
let NumMicroOps = 4;
}
@@ -2669,7 +2669,7 @@ def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rm
def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rm)>;
def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 10;
let NumMicroOps = 4;
}
@@ -2677,7 +2677,7 @@ def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault
def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrm)>;
def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 3;
let NumMicroOps = 3;
}
@@ -2686,7 +2686,7 @@ def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rr$",
"^VPBLENDVB(Y?)rr$")>;
def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 9;
let NumMicroOps = 4;
}
@@ -2750,7 +2750,7 @@ def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
def : InstRW<[SPRWriteResGroup264, ReadAfterVecLd], (instregex "^V(U?)COMISHZrm((_Int)?)$")>;
def SPRWriteResGroup265 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 12;
let NumMicroOps = 4;
}
@@ -2764,7 +2764,7 @@ def : InstRW<[SPRWriteResGroup265], (instregex "^VCOMPRESSP(D|S)Z(128|256)mr$",
"^VPMOVUS(Q|W)BZmr$")>;
def SPRWriteResGroup266 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 15;
let NumMicroOps = 4;
}
@@ -2778,7 +2778,7 @@ def : InstRW<[SPRWriteResGroup266], (instregex "^VCOMPRESSP(D|S)Z(128|256)mrk$",
"^VPMOVUS(Q|W)BZmrk$")>;
def SPRWriteResGroup267 : SchedWriteRes<[SPRPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 3;
let NumMicroOps = 2;
}
@@ -2855,14 +2855,14 @@ def SPRWriteResGroup276 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]>
def : InstRW<[SPRWriteResGroup276], (instregex "^VCVT(U?)DQ2PHZ256rrk(z?)$")>;
def SPRWriteResGroup277 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 17;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup277], (instregex "^VCVT(U?)DQ2PHZrm(b?)$")>;
def SPRWriteResGroup278 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 21;
let NumMicroOps = 4;
}
@@ -2870,14 +2870,14 @@ def : InstRW<[SPRWriteResGroup278], (instregex "^VCVT(U?)DQ2PHZrm(bk|kz)$",
"^VCVT(U?)DQ2PHZrm(k|bkz)$")>;
def SPRWriteResGroup279 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 9;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup279], (instregex "^VCVT(U?)DQ2PHZrr(b?)$")>;
def SPRWriteResGroup280 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 14;
let NumMicroOps = 3;
}
@@ -2885,14 +2885,14 @@ def : InstRW<[SPRWriteResGroup280], (instregex "^VCVT(U?)DQ2PHZrr(bk|kz)$",
"^VCVT(U?)DQ2PHZrr(k|bkz)$")>;
def SPRWriteResGroup281 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1];
let Latency = 15;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup281, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(b?)$")>;
def SPRWriteResGroup282 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 5;
}
@@ -2900,28 +2900,28 @@ def : InstRW<[SPRWriteResGroup282, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16
"^VCVTNE2PS2BF16Z128rm(k|bkz)$")>;
def SPRWriteResGroup283 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 8;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup283], (instregex "^VCVTNE2PS2BF16Z(128|256)rr$")>;
def SPRWriteResGroup284 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 10;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup284], (instregex "^VCVTNE2PS2BF16Z(128|256)rrk(z?)$")>;
def SPRWriteResGroup285 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1];
let Latency = 16;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup285, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(b?)$")>;
def SPRWriteResGroup286 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1];
+ let ResourceCycles = [2, 1, 1, 1];
let Latency = 18;
let NumMicroOps = 5;
}
@@ -2929,7 +2929,7 @@ def : InstRW<[SPRWriteResGroup286, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16
"^VCVTNE2PS2BF16Z256rm(k|bkz)$")>;
def SPRWriteResGroup287 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 16;
let NumMicroOps = 5;
}
@@ -2938,7 +2938,7 @@ def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16
def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instrs VDPBF16PSZmbkz)>;
def SPRWriteResGroup288 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 18;
let NumMicroOps = 5;
}
@@ -2946,7 +2946,7 @@ def : InstRW<[SPRWriteResGroup288, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16
"^VCVTNE2PS2BF16Zrm(k|bkz)$")>;
def SPRWriteResGroup289 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 8;
let NumMicroOps = 4;
}
@@ -2954,7 +2954,7 @@ def : InstRW<[SPRWriteResGroup289], (instregex "^VDPBF16PSZr((k|kz)?)$")>;
def : InstRW<[SPRWriteResGroup289], (instrs VCVTNE2PS2BF16Zrr)>;
def SPRWriteResGroup290 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 10;
let NumMicroOps = 4;
}
@@ -2986,14 +2986,14 @@ def : InstRW<[SPRWriteResGroup294], (instregex "^VCVTNEPS2BF16Z256rm(bk|kz)$",
"^VCVTNEPS2BF16Z256rm(k|bkz)$")>;
def SPRWriteResGroup295 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 16;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup295], (instregex "^VCVTNEPS2BF16Zrm(b?)$")>;
def SPRWriteResGroup296 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 18;
let NumMicroOps = 4;
}
@@ -3001,14 +3001,14 @@ def : InstRW<[SPRWriteResGroup296], (instregex "^VCVTNEPS2BF16Zrm(bk|kz)$",
"^VCVTNEPS2BF16Zrm(k|bkz)$")>;
def SPRWriteResGroup297 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 8;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup297], (instrs VCVTNEPS2BF16Zrr)>;
def SPRWriteResGroup298 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 10;
let NumMicroOps = 3;
}
@@ -3040,14 +3040,14 @@ def : InstRW<[SPRWriteResGroup300], (instregex "^VCVT(T?)P(D|H)2(U?)DQZrm(b?)$",
"^VCVT(U?)QQ2PSZrmbkz$")>;
def SPRWriteResGroup301 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 1, 2];
let Latency = 19;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup301], (instregex "^VCVTPD2PHZ128rm(b?)$")>;
def SPRWriteResGroup302 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 1, 2];
let Latency = 22;
let NumMicroOps = 7;
}
@@ -3055,28 +3055,28 @@ def : InstRW<[SPRWriteResGroup302], (instregex "^VCVTPD2PHZ128rm(bk|kz)$",
"^VCVTPD2PHZ128rm(k|bkz)$")>;
def SPRWriteResGroup303 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 12;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup303], (instrs VCVTPD2PHZ128rr)>;
def SPRWriteResGroup304 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 15;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup304], (instregex "^VCVTPD2PHZ128rrk(z?)$")>;
def SPRWriteResGroup305 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 21;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup305], (instregex "^VCVTPD2PHZ256rm(b?)$")>;
def SPRWriteResGroup306 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 24;
let NumMicroOps = 6;
}
@@ -3084,28 +3084,28 @@ def : InstRW<[SPRWriteResGroup306], (instregex "^VCVTPD2PHZ256rm(bk|kz)$",
"^VCVTPD2PHZ256rm(k|bkz)$")>;
def SPRWriteResGroup307 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 13;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup307], (instrs VCVTPD2PHZ256rr)>;
def SPRWriteResGroup308 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 16;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup308], (instregex "^VCVTPD2PHZ256rrk(z?)$")>;
def SPRWriteResGroup309 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 23;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup309], (instregex "^VCVTP(D2PH|H2PD)Zrm(b?)$")>;
def SPRWriteResGroup310 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 26;
let NumMicroOps = 6;
}
@@ -3113,14 +3113,14 @@ def : InstRW<[SPRWriteResGroup310], (instregex "^VCVTP(D2PH|H2PD)Zrm(bk|kz)$",
"^VCVTP(D2PH|H2PD)Zrm(k|bkz)$")>;
def SPRWriteResGroup311 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 15;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup311], (instregex "^VCVTP(D2PH|H2PD)Zrr(b?)$")>;
def SPRWriteResGroup312 : SchedWriteRes<[SPRPort00, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 18;
let NumMicroOps = 4;
}
@@ -3227,14 +3227,14 @@ def : InstRW<[SPRWriteResGroup321], (instregex "^VCVT(T?)PH2(U?)DQZrr(bk|kz)$",
"^VCVTP(H2PS|S2PH)XZrr(k|bkz)$")>;
def SPRWriteResGroup322 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 1, 2];
let Latency = 23;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup322], (instregex "^VCVTPH2PDZ128rm(b?)$")>;
def SPRWriteResGroup323 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 1, 2];
let Latency = 26;
let NumMicroOps = 7;
}
@@ -3242,28 +3242,28 @@ def : InstRW<[SPRWriteResGroup323], (instregex "^VCVTPH2PDZ128rm(bk|kz)$",
"^VCVTPH2PDZ128rm(k|bkz)$")>;
def SPRWriteResGroup324 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 16;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup324], (instrs VCVTPH2PDZ128rr)>;
def SPRWriteResGroup325 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1, 2];
+ let ResourceCycles = [2, 1, 1, 2];
let Latency = 19;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup325], (instregex "^VCVTPH2PDZ128rrk(z?)$")>;
def SPRWriteResGroup326 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 22;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup326], (instregex "^VCVTPH2PDZ256rm(b?)$")>;
def SPRWriteResGroup327 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 25;
let NumMicroOps = 5;
}
@@ -3271,14 +3271,14 @@ def : InstRW<[SPRWriteResGroup327], (instregex "^VCVTPH2PDZ256rm(bk|kz)$",
"^VCVTPH2PDZ256rm(k|bkz)$")>;
def SPRWriteResGroup328 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 15;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup328], (instrs VCVTPH2PDZ256rr)>;
def SPRWriteResGroup329 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 18;
let NumMicroOps = 4;
}
@@ -3313,7 +3313,7 @@ def : InstRW<[SPRWriteResGroup332], (instrs VCVTPH2PSZrm)>;
def : InstRW<[SPRWriteResGroup332, ReadAfterVecYLd], (instregex "^VPERMWZrmk(z?)$")>;
def SPRWriteResGroup333 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2, 1, 1, 1];
+ let ResourceCycles = [1, 2, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 6;
}
@@ -3321,14 +3321,14 @@ def : InstRW<[SPRWriteResGroup333], (instregex "^VCVT(T?)PH2(U?)QQZ128rm((b|k|bk
"^VCVT(T?)PH2(U?)QQZ128rmbkz$")>;
def SPRWriteResGroup334 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 10;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup334], (instregex "^VCVT(T?)PH2(U?)QQZ(128|256)rr((k|kz)?)$")>;
def SPRWriteResGroup335 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2, 1, 1, 1];
+ let ResourceCycles = [1, 2, 1, 1, 1];
let Latency = 18;
let NumMicroOps = 6;
}
@@ -3414,14 +3414,14 @@ def SPRWriteResGroup347 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort0
def : InstRW<[SPRWriteResGroup347], (instregex "^VCVT(U?)QQ2PHZ256rrk(z?)$")>;
def SPRWriteResGroup348 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 1, 2];
+ let ResourceCycles = [1, 1, 1, 2];
let Latency = 18;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup348], (instregex "^VCVT(U?)QQ2PHZrm(b?)$")>;
def SPRWriteResGroup349 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 1, 2];
+ let ResourceCycles = [1, 1, 1, 2];
let Latency = 20;
let NumMicroOps = 5;
}
@@ -3429,14 +3429,14 @@ def : InstRW<[SPRWriteResGroup349], (instregex "^VCVT(U?)QQ2PHZrm(bk|kz)$",
"^VCVT(U?)QQ2PHZrm(k|bkz)$")>;
def SPRWriteResGroup350 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 10;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup350], (instregex "^VCVT(U?)QQ2PHZrr(b?)$")>;
def SPRWriteResGroup351 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 12;
let NumMicroOps = 4;
}
@@ -3444,21 +3444,21 @@ def : InstRW<[SPRWriteResGroup351], (instregex "^VCVT(U?)QQ2PHZrr(bk|kz)$",
"^VCVT(U?)QQ2PHZrr(k|bkz)$")>;
def SPRWriteResGroup352 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 2, 1, 1, 1];
+ let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = 18;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup352, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm((_Int)?)$")>;
def SPRWriteResGroup353 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 2, 1, 1, 1];
+ let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = 21;
let NumMicroOps = 7;
}
def : InstRW<[SPRWriteResGroup353, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm_Intk(z?)$")>;
def SPRWriteResGroup354 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 11;
let NumMicroOps = 4;
}
@@ -3466,28 +3466,28 @@ def : InstRW<[SPRWriteResGroup354], (instregex "^VCVTSD2SHZrr(b?)_Int$")>;
def : InstRW<[SPRWriteResGroup354], (instrs VCVTSD2SHZrr)>;
def SPRWriteResGroup355 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 14;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup355], (instregex "^VCVTSD2SHZrr(b?)_Intk(z?)$")>;
def SPRWriteResGroup356 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 18;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup356, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm((_Int)?)$")>;
def SPRWriteResGroup357 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 20;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup357, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm_Intk(z?)$")>;
def SPRWriteResGroup358 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 10;
let NumMicroOps = 3;
}
@@ -3495,7 +3495,7 @@ def : InstRW<[SPRWriteResGroup358], (instregex "^VCVTSH2SDZrr(b?)_Int$")>;
def : InstRW<[SPRWriteResGroup358], (instrs VCVTSH2SDZrr)>;
def SPRWriteResGroup359 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 13;
let NumMicroOps = 3;
}
@@ -3568,14 +3568,14 @@ def : InstRW<[SPRWriteResGroup367], (instregex "^VDBPSADBWZ(128|256)rrik(z?)$",
"^VPOPCNT(B|W)Zrrk(z?)$")>;
def SPRWriteResGroup368 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 36;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup368, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b?)$")>;
def SPRWriteResGroup369 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 38;
let NumMicroOps = 4;
}
@@ -3583,14 +3583,14 @@ def : InstRW<[SPRWriteResGroup369, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b
"^VDIVPHZ128rm(k|bkz)$")>;
def SPRWriteResGroup370 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 31;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup370], (instregex "^VDIVPHZ(128|256)rr$")>;
def SPRWriteResGroup371 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 33;
let NumMicroOps = 3;
}
@@ -3599,14 +3599,14 @@ def : InstRW<[SPRWriteResGroup371], (instregex "^VDIVPHZ(128|256)rrk$",
def : InstRW<[SPRWriteResGroup371], (instrs VDIVPHZ128rrkz)>;
def SPRWriteResGroup372 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 37;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup372, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b?)$")>;
def SPRWriteResGroup373 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 39;
let NumMicroOps = 4;
}
@@ -3615,21 +3615,21 @@ def : InstRW<[SPRWriteResGroup373, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b
def : InstRW<[SPRWriteResGroup373, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b?)$")>;
def SPRWriteResGroup374 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 11;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup374], (instrs VDIVPHZ256rrkz)>;
def SPRWriteResGroup375 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1];
let Latency = 49;
let NumMicroOps = 9;
}
def : InstRW<[SPRWriteResGroup375, ReadAfterVecYLd], (instregex "^VDIVPHZrm(b?)$")>;
def SPRWriteResGroup376 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1];
let Latency = 51;
let NumMicroOps = 9;
}
@@ -3637,14 +3637,14 @@ def : InstRW<[SPRWriteResGroup376, ReadAfterVecYLd], (instregex "^VDIVPHZrm(bk|k
"^VDIVPHZrm(k|bkz)$")>;
def SPRWriteResGroup377 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let Latency = 41;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup377], (instregex "^VDIVPHZrr(b?)$")>;
def SPRWriteResGroup378 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let Latency = 43;
let NumMicroOps = 6;
}
@@ -3652,7 +3652,7 @@ def : InstRW<[SPRWriteResGroup378], (instregex "^VDIVPHZrr(bk|kz)$",
"^VDIVPHZrr(k|bkz)$")>;
def SPRWriteResGroup379 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 17;
let NumMicroOps = 3;
}
@@ -3672,7 +3672,7 @@ def : InstRW<[SPRWriteResGroup381], (instrs VDIVSHZrr_Int,
VSQRTSHZr_Int)>;
def SPRWriteResGroup382 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 15;
let NumMicroOps = 5;
}
@@ -3680,14 +3680,14 @@ def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instregex "^VDPBF16PSZ128m
def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instrs VDPBF16PSZ128mbkz)>;
def SPRWriteResGroup383 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
- let ReleaseAtCycles = [2, 2];
+ let ResourceCycles = [2, 2];
let Latency = 8;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup383], (instregex "^VDPBF16PSZ(128|256)r((k|kz)?)$")>;
def SPRWriteResGroup384 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 2];
+ let ResourceCycles = [2, 1, 2];
let Latency = 16;
let NumMicroOps = 5;
}
@@ -3695,35 +3695,35 @@ def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instregex "^VDPBF16PSZ256m
def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instrs VDPBF16PSZ256mbkz)>;
def SPRWriteResGroup385 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [6, 7, 18];
+ let ResourceCycles = [6, 7, 18];
let Latency = 81;
let NumMicroOps = 31;
}
def : InstRW<[SPRWriteResGroup385], (instrs VERRm)>;
def SPRWriteResGroup386 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [6, 7, 17];
+ let ResourceCycles = [6, 7, 17];
let Latency = 74;
let NumMicroOps = 30;
}
def : InstRW<[SPRWriteResGroup386], (instrs VERRr)>;
def SPRWriteResGroup387 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [5, 8, 21];
+ let ResourceCycles = [5, 8, 21];
let Latency = 81;
let NumMicroOps = 34;
}
def : InstRW<[SPRWriteResGroup387], (instrs VERWm)>;
def SPRWriteResGroup388 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [5, 8, 20];
+ let ResourceCycles = [5, 8, 20];
let Latency = 74;
let NumMicroOps = 33;
}
def : InstRW<[SPRWriteResGroup388], (instrs VERWr)>;
def SPRWriteResGroup389 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 10;
let NumMicroOps = 3;
}
@@ -3732,7 +3732,7 @@ def : InstRW<[SPRWriteResGroup389, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z
"^VPEXPAND(D|Q)Z128rmk(z?)$")>;
def SPRWriteResGroup390 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 16;
let NumMicroOps = 3;
}
@@ -3751,7 +3751,7 @@ def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ2
def : InstRW<[SPRWriteResGroup390, ReadAfterVecLd], (instrs VSCALEFSHZrm)>;
def SPRWriteResGroup391 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 21;
let NumMicroOps = 3;
}
@@ -3765,7 +3765,7 @@ def : InstRW<[SPRWriteResGroup391, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ2
"^VF(C?)MULCPHZ256rm(k|bkz)$")>;
def SPRWriteResGroup392 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 9;
let NumMicroOps = 2;
}
@@ -3781,7 +3781,7 @@ def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZr,
VSCALEFSHZrrb_Int)>;
def SPRWriteResGroup393 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 15;
let NumMicroOps = 2;
}
@@ -3793,7 +3793,7 @@ def : InstRW<[SPRWriteResGroup393], (instregex "^VF(C?)MADDCPHZ(128|256)rk(z?)$"
"^VF(C?)MULCSHZrr(k|bkz)$")>;
def SPRWriteResGroup394 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 16;
let NumMicroOps = 3;
}
@@ -3804,7 +3804,7 @@ def : InstRW<[SPRWriteResGroup394, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZr
"^VSCALEFPHZrm(b?)$")>;
def SPRWriteResGroup395 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 21;
let NumMicroOps = 3;
}
@@ -3814,7 +3814,7 @@ def : InstRW<[SPRWriteResGroup395, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZr
"^VF(C?)MULCPHZrm(k|bkz)$")>;
def SPRWriteResGroup396 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 9;
let NumMicroOps = 2;
}
@@ -3824,7 +3824,7 @@ def : InstRW<[SPRWriteResGroup396], (instregex "^VF(C?)MADDCPHZr(b?)$",
"^VSCALEFPHZrr(b?)$")>;
def SPRWriteResGroup397 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 15;
let NumMicroOps = 2;
}
@@ -3834,7 +3834,7 @@ def : InstRW<[SPRWriteResGroup397], (instregex "^VF(C?)MADDCPHZr(bk|kz)$",
"^VF(C?)MULCPHZrr(k|bkz)$")>;
def SPRWriteResGroup398 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 4];
+ let ResourceCycles = [1, 1, 2, 4];
let Latency = 29;
let NumMicroOps = 8;
}
@@ -3844,7 +3844,7 @@ def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERQDYrm)>;
def SPRWriteResGroup399 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 20;
let NumMicroOps = 4;
}
@@ -3854,7 +3854,7 @@ def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERQDZ128rm)>;
def SPRWriteResGroup400 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 4];
+ let ResourceCycles = [1, 2, 4];
let Latency = 28;
let NumMicroOps = 7;
}
@@ -3864,7 +3864,7 @@ def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERQDZ256rm)>;
def SPRWriteResGroup401 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 8, 2];
+ let ResourceCycles = [1, 8, 2];
let Latency = 28;
let NumMicroOps = 11;
}
@@ -3874,7 +3874,7 @@ def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERQDZrm)>;
def SPRWriteResGroup402 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 1, 2];
+ let ResourceCycles = [1, 1, 1, 2];
let Latency = 20;
let NumMicroOps = 5;
}
@@ -3884,7 +3884,7 @@ def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERQDrm)>;
def SPRWriteResGroup403 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 8];
+ let ResourceCycles = [1, 1, 2, 8];
let Latency = 30;
let NumMicroOps = 12;
}
@@ -3892,7 +3892,7 @@ def : InstRW<[SPRWriteResGroup403, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERDDYrm)>;
def SPRWriteResGroup404 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 4];
+ let ResourceCycles = [1, 2, 4];
let Latency = 27;
let NumMicroOps = 7;
}
@@ -3900,7 +3900,7 @@ def : InstRW<[SPRWriteResGroup404, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERDDZ128rm)>;
def SPRWriteResGroup405 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 8];
+ let ResourceCycles = [1, 2, 8];
let Latency = 29;
let NumMicroOps = 11;
}
@@ -3908,7 +3908,7 @@ def : InstRW<[SPRWriteResGroup405, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERDDZ256rm)>;
def SPRWriteResGroup406 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 16, 2];
+ let ResourceCycles = [1, 16, 2];
let Latency = 30;
let NumMicroOps = 19;
}
@@ -3916,7 +3916,7 @@ def : InstRW<[SPRWriteResGroup406, WriteVecMaskedGatherWriteback], (instrs VGATH
VPGATHERDDZrm)>;
def SPRWriteResGroup407 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 1, 2, 4];
+ let ResourceCycles = [1, 1, 2, 4];
let Latency = 28;
let NumMicroOps = 8;
}
@@ -3964,7 +3964,7 @@ def : InstRW<[SPRWriteResGroup413], (instregex "^VGF2P8AFFINE((INV)?)QBZrrikz$")
def : InstRW<[SPRWriteResGroup413], (instrs VGF2P8MULBZrrkz)>;
def SPRWriteResGroup414 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 5;
let NumMicroOps = 3;
}
@@ -3977,7 +3977,7 @@ def SPRWriteResGroup415 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_1
def : InstRW<[SPRWriteResGroup415], (instrs VLDMXCSR)>;
def SPRWriteResGroup416 : SchedWriteRes<[SPRPort01, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
- let ReleaseAtCycles = [1, 1, 1, 8, 1, 1, 2, 3];
+ let ResourceCycles = [1, 1, 1, 8, 1, 1, 2, 3];
let Latency = 40;
let NumMicroOps = 18;
}
@@ -4004,7 +4004,7 @@ def : InstRW<[SPRWriteResGroup418], (instregex "^VMOVDQU(8|16)Z(128|256)rrk(z?)(
"^VPMOVM2(B|W)Z(128|256)rr$")>;
def SPRWriteResGroup419 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 2, 2];
+ let ResourceCycles = [1, 2, 2];
let Latency = 12;
let NumMicroOps = 5;
}
@@ -4078,7 +4078,7 @@ def SPRWriteResGroup430 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
def : InstRW<[SPRWriteResGroup430], (instrs VMOVNTPSZmr)>;
def SPRWriteResGroup431 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [3, 1, 8];
+ let ResourceCycles = [3, 1, 8];
let Latency = 10;
let NumMicroOps = 12;
}
@@ -4086,7 +4086,7 @@ def : InstRW<[SPRWriteResGroup431, ReadAfterVecXLd], (instregex "^VP2INTERSECTDZ
def : InstRW<[SPRWriteResGroup431, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZ256rm(b?)$")>;
def SPRWriteResGroup432 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [4, 8];
+ let ResourceCycles = [4, 8];
let Latency = 10;
let NumMicroOps = 12;
}
@@ -4094,56 +4094,56 @@ def : InstRW<[SPRWriteResGroup432], (instrs VP2INTERSECTDZ128rr,
VP2INTERSECTQZ256rr)>;
def SPRWriteResGroup433 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 8, 7, 2, 1, 11];
+ let ResourceCycles = [1, 8, 7, 2, 1, 11];
let Latency = 27;
let NumMicroOps = 30;
}
def : InstRW<[SPRWriteResGroup433, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZ256rm(b?)$")>;
def SPRWriteResGroup434 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 8, 8, 2, 11];
+ let ResourceCycles = [1, 8, 8, 2, 11];
let Latency = 27;
let NumMicroOps = 30;
}
def : InstRW<[SPRWriteResGroup434], (instrs VP2INTERSECTDZ256rr)>;
def SPRWriteResGroup435 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [13, 9, 1, 23];
+ let ResourceCycles = [13, 9, 1, 23];
let Latency = 40;
let NumMicroOps = 46;
}
def : InstRW<[SPRWriteResGroup435, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZrm(b?)$")>;
def SPRWriteResGroup436 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [13, 10, 23];
+ let ResourceCycles = [13, 10, 23];
let Latency = 40;
let NumMicroOps = 46;
}
def : InstRW<[SPRWriteResGroup436], (instrs VP2INTERSECTDZrr)>;
def SPRWriteResGroup437 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 4];
+ let ResourceCycles = [1, 4];
let Latency = 6;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup437, ReadAfterVecXLd], (instregex "^VP2INTERSECTQZ128rm(b?)$")>;
def SPRWriteResGroup438 : SchedWriteRes<[SPRPort05]> {
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let Latency = 6;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup438], (instrs VP2INTERSECTQZ128rr)>;
def SPRWriteResGroup439 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [8, 7, 1, 14];
+ let ResourceCycles = [8, 7, 1, 14];
let Latency = 29;
let NumMicroOps = 30;
}
def : InstRW<[SPRWriteResGroup439, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZrm(b?)$")>;
def SPRWriteResGroup440 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [8, 8, 14];
+ let ResourceCycles = [8, 8, 14];
let Latency = 30;
let NumMicroOps = 30;
}
@@ -4186,7 +4186,7 @@ def : InstRW<[SPRWriteResGroup443], (instregex "^VPBROADCASTM(B2Q|W2D)Z(128|256)
def : InstRW<[SPRWriteResGroup443], (instrs VPSHUFBITQMBZrr)>;
def SPRWriteResGroup444 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 1, 2, 1];
+ let ResourceCycles = [1, 1, 1, 2, 1];
let Latency = 12;
let NumMicroOps = 6;
}
@@ -4194,7 +4194,7 @@ def : InstRW<[SPRWriteResGroup444], (instregex "^VPCOMPRESS(B|W)Z(128|256)mr$")>
def : InstRW<[SPRWriteResGroup444], (instrs VPCOMPRESSWZmr)>;
def SPRWriteResGroup445 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 1, 2, 1];
+ let ResourceCycles = [1, 1, 1, 2, 1];
let Latency = 14;
let NumMicroOps = 6;
}
@@ -4202,21 +4202,21 @@ def : InstRW<[SPRWriteResGroup445], (instregex "^VPCOMPRESS(B|W)Z(128|256)mrk$")
def : InstRW<[SPRWriteResGroup445], (instrs VPCOMPRESSWZmrk)>;
def SPRWriteResGroup446 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 2, 2, 2];
+ let ResourceCycles = [1, 1, 2, 2, 2];
let Latency = 12;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup446], (instrs VPCOMPRESSBZmr)>;
def SPRWriteResGroup447 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 2, 2, 2];
+ let ResourceCycles = [1, 1, 2, 2, 2];
let Latency = 14;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup447], (instrs VPCOMPRESSBZmrk)>;
def SPRWriteResGroup448 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [5, 4, 1, 5];
+ let ResourceCycles = [5, 4, 1, 5];
let Latency = 17;
let NumMicroOps = 15;
}
@@ -4224,14 +4224,14 @@ def : InstRW<[SPRWriteResGroup448], (instregex "^VPCONFLICTDZ128rm((b|k|bk|kz)?)
def : InstRW<[SPRWriteResGroup448], (instrs VPCONFLICTDZ128rmbkz)>;
def SPRWriteResGroup449 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [5, 5, 5];
+ let ResourceCycles = [5, 5, 5];
let Latency = 12;
let NumMicroOps = 15;
}
def : InstRW<[SPRWriteResGroup449], (instregex "^VPCONFLICTDZ128rr((k|kz)?)$")>;
def SPRWriteResGroup450 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 5, 1, 1, 9];
+ let ResourceCycles = [7, 5, 1, 1, 9];
let Latency = 24;
let NumMicroOps = 23;
}
@@ -4239,14 +4239,14 @@ def : InstRW<[SPRWriteResGroup450], (instregex "^VPCONFLICTDZ256rm((b|k|bk|kz)?)
def : InstRW<[SPRWriteResGroup450], (instrs VPCONFLICTDZ256rmbkz)>;
def SPRWriteResGroup451 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 1, 9];
+ let ResourceCycles = [7, 6, 1, 9];
let Latency = 17;
let NumMicroOps = 23;
}
def : InstRW<[SPRWriteResGroup451], (instregex "^VPCONFLICTDZ256rr((k|kz)?)$")>;
def SPRWriteResGroup452 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [11, 8, 1, 17];
+ let ResourceCycles = [11, 8, 1, 17];
let Latency = 33;
let NumMicroOps = 37;
}
@@ -4254,21 +4254,21 @@ def : InstRW<[SPRWriteResGroup452], (instregex "^VPCONFLICTDZrm((b|k|bk|kz)?)$")
def : InstRW<[SPRWriteResGroup452], (instrs VPCONFLICTDZrmbkz)>;
def SPRWriteResGroup453 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [11, 9, 17];
+ let ResourceCycles = [11, 9, 17];
let Latency = 26;
let NumMicroOps = 37;
}
def : InstRW<[SPRWriteResGroup453], (instregex "^VPCONFLICTDZrr((kz)?)$")>;
def SPRWriteResGroup454 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [11, 9, 17];
+ let ResourceCycles = [11, 9, 17];
let Latency = 25;
let NumMicroOps = 37;
}
def : InstRW<[SPRWriteResGroup454], (instrs VPCONFLICTDZrrk)>;
def SPRWriteResGroup455 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 11;
let NumMicroOps = 4;
}
@@ -4277,14 +4277,14 @@ def : InstRW<[SPRWriteResGroup455], (instrs VPCONFLICTQZ128rmbkz)>;
def : InstRW<[SPRWriteResGroup455, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B128rm$")>;
def SPRWriteResGroup456 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 4;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup456], (instregex "^VPCONFLICTQZ128rr((k|kz)?)$")>;
def SPRWriteResGroup457 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [5, 4, 1, 5];
+ let ResourceCycles = [5, 4, 1, 5];
let Latency = 20;
let NumMicroOps = 15;
}
@@ -4292,14 +4292,14 @@ def : InstRW<[SPRWriteResGroup457], (instregex "^VPCONFLICTQZ256rm((b|k|bk|kz)?)
def : InstRW<[SPRWriteResGroup457], (instrs VPCONFLICTQZ256rmbkz)>;
def SPRWriteResGroup458 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [5, 5, 5];
+ let ResourceCycles = [5, 5, 5];
let Latency = 13;
let NumMicroOps = 15;
}
def : InstRW<[SPRWriteResGroup458], (instregex "^VPCONFLICTQZ256rr((k|kz)?)$")>;
def SPRWriteResGroup459 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [7, 5, 1, 9];
+ let ResourceCycles = [7, 5, 1, 9];
let Latency = 23;
let NumMicroOps = 22;
}
@@ -4307,21 +4307,21 @@ def : InstRW<[SPRWriteResGroup459], (instregex "^VPCONFLICTQZrm((b|k|bk|kz)?)$")
def : InstRW<[SPRWriteResGroup459], (instrs VPCONFLICTQZrmbkz)>;
def SPRWriteResGroup460 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 9];
+ let ResourceCycles = [7, 6, 9];
let Latency = 17;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup460], (instregex "^VPCONFLICTQZrr((kz)?)$")>;
def SPRWriteResGroup461 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [7, 6, 9];
+ let ResourceCycles = [7, 6, 9];
let Latency = 16;
let NumMicroOps = 22;
}
def : InstRW<[SPRWriteResGroup461], (instrs VPCONFLICTQZrrk)>;
def SPRWriteResGroup462 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 13;
let NumMicroOps = 4;
}
@@ -4329,14 +4329,14 @@ def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B12
def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instrs VPERMT2W128rm)>;
def SPRWriteResGroup463 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 5;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup463], (instregex "^VPERM(I|T)2B(128|256)rr$")>;
def SPRWriteResGroup464 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 7;
let NumMicroOps = 3;
}
@@ -4344,14 +4344,14 @@ def : InstRW<[SPRWriteResGroup464], (instregex "^VPERM(I|T)2B(128|256)rrk(z?)$",
"^VPERM(I|T)2W(128|256)rr$")>;
def SPRWriteResGroup465 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 12;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup465, ReadAfterVecYLd], (instregex "^VPERM(I|T)2B256rm$")>;
def SPRWriteResGroup466 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 14;
let NumMicroOps = 4;
}
@@ -4360,14 +4360,14 @@ def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instrs VPERMI2W128rm,
VPERMT2W256rm)>;
def SPRWriteResGroup467 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 12;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup467, ReadAfterVecYLd], (instregex "^VPERM(I|T)2Brm$")>;
def SPRWriteResGroup468 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 14;
let NumMicroOps = 4;
}
@@ -4375,14 +4375,14 @@ def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instregex "^VPERM(I|T)2Brm
def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instrs VPERMT2Wrm)>;
def SPRWriteResGroup469 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 5;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup469], (instregex "^VPERM(I|T)2Brr$")>;
def SPRWriteResGroup470 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 7;
let NumMicroOps = 3;
}
@@ -4390,7 +4390,7 @@ def : InstRW<[SPRWriteResGroup470], (instregex "^VPERM(I|T)2Brrk(z?)$",
"^VPERM(I|T)2Wrr$")>;
def SPRWriteResGroup471 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 16;
let NumMicroOps = 4;
}
@@ -4398,14 +4398,14 @@ def : InstRW<[SPRWriteResGroup471, ReadAfterVecYLd], (instregex "^VPERMI2W128rmk
"^VPERMT2W256rmk(z?)$")>;
def SPRWriteResGroup472 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 9;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup472], (instregex "^VPERM(I|T)2W(128|256)rrk(z?)$")>;
def SPRWriteResGroup473 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 15;
let NumMicroOps = 4;
}
@@ -4413,35 +4413,35 @@ def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instregex "^VPERMT2W128rmk
def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instrs VPERMI2W256rm)>;
def SPRWriteResGroup474 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 17;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup474, ReadAfterVecYLd], (instregex "^VPERMI2W256rmk(z?)$")>;
def SPRWriteResGroup475 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 15;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup475, ReadAfterVecYLd], (instrs VPERMI2Wrm)>;
def SPRWriteResGroup476 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 17;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup476, ReadAfterVecYLd], (instregex "^VPERMI2Wrmk(z?)$")>;
def SPRWriteResGroup477 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let Latency = 9;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup477], (instregex "^VPERM(I|T)2Wrrk(z?)$")>;
def SPRWriteResGroup478 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let Latency = 16;
let NumMicroOps = 4;
}
@@ -4478,7 +4478,7 @@ def SPRWriteResGroup483 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]>
def : InstRW<[SPRWriteResGroup483, ReadAfterVecYLd], (instrs VPERMWZrm)>;
def SPRWriteResGroup484 : SchedWriteRes<[SPRPort05]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 8;
let NumMicroOps = 2;
}
@@ -4486,7 +4486,7 @@ def : InstRW<[SPRWriteResGroup484], (instregex "^VPEXPAND(B|W)Z(128|256)rrk(z?)$
"^VPEXPAND(B|W)Zrrk(z?)$")>;
def SPRWriteResGroup485 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [1, 2, 1];
+ let ResourceCycles = [1, 2, 1];
let Latency = 10;
let NumMicroOps = 4;
}
@@ -4591,7 +4591,7 @@ def SPRWriteResGroup496 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]>
def : InstRW<[SPRWriteResGroup496], (instregex "^VPMOVQDZ((256)?)mrk$")>;
def SPRWriteResGroup497 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 23;
let NumMicroOps = 4;
}
@@ -4601,14 +4601,14 @@ def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instregex "^VPMULLQZ256rm(
def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instrs VPMULLQZ256rmbkz)>;
def SPRWriteResGroup498 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 15;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup498], (instregex "^VPMULLQZ(128|256)rr((k|kz)?)$")>;
def SPRWriteResGroup499 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 23;
let NumMicroOps = 4;
}
@@ -4616,14 +4616,14 @@ def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instregex "^VPMULLQZrm((b|
def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instrs VPMULLQZrmbkz)>;
def SPRWriteResGroup500 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 15;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup500], (instregex "^VPMULLQZrr((k|kz)?)$")>;
def SPRWriteResGroup501 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 1, 4, 4];
+ let ResourceCycles = [1, 1, 1, 4, 4];
let Latency = 12;
let NumMicroOps = 11;
}
@@ -4635,7 +4635,7 @@ def : InstRW<[SPRWriteResGroup501], (instrs VPSCATTERDDZ128mr,
VSCATTERQPSZ256mr)>;
def SPRWriteResGroup502 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 1, 8, 8];
+ let ResourceCycles = [1, 1, 1, 8, 8];
let Latency = 12;
let NumMicroOps = 19;
}
@@ -4643,7 +4643,7 @@ def : InstRW<[SPRWriteResGroup502], (instrs VPSCATTERDDZ256mr,
VSCATTERDPSZ256mr)>;
def SPRWriteResGroup503 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 16, 16];
+ let ResourceCycles = [2, 1, 16, 16];
let Latency = 19;
let NumMicroOps = 35;
}
@@ -4651,7 +4651,7 @@ def : InstRW<[SPRWriteResGroup503], (instrs VPSCATTERDDZmr,
VSCATTERDPSZmr)>;
def SPRWriteResGroup504 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 1, 1, 2, 2];
+ let ResourceCycles = [1, 1, 1, 2, 2];
let Latency = 12;
let NumMicroOps = 7;
}
@@ -4661,7 +4661,7 @@ def : InstRW<[SPRWriteResGroup504], (instrs VPSCATTERQDZ128mr,
VSCATTERQPSZ128mr)>;
def SPRWriteResGroup505 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
- let ReleaseAtCycles = [2, 1, 8, 8];
+ let ResourceCycles = [2, 1, 8, 8];
let Latency = 12;
let NumMicroOps = 19;
}
@@ -4787,7 +4787,7 @@ def : InstRW<[SPRWriteResGroup522], (instregex "^VPS(L|R)LWZ128rrk(z?)$",
"^VPSRAWZ128rrk(z?)$")>;
def SPRWriteResGroup523 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 16;
let NumMicroOps = 4;
}
@@ -4795,14 +4795,14 @@ def : InstRW<[SPRWriteResGroup523, ReadAfterVecYLd], (instregex "^VR(CP|SQRT)PHZ
"^VR(CP|SQRT)PHZm(k|bkz)$")>;
def SPRWriteResGroup524 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 9;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup524], (instregex "^VRCPPHZrk(z?)$")>;
def SPRWriteResGroup525 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 20;
let NumMicroOps = 4;
}
@@ -4811,7 +4811,7 @@ def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instrs VREDUCESHZrmi)>;
def : InstRW<[SPRWriteResGroup525, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)i$")>;
def SPRWriteResGroup526 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 22;
let NumMicroOps = 4;
}
@@ -4820,7 +4820,7 @@ def : InstRW<[SPRWriteResGroup526, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128r
def : InstRW<[SPRWriteResGroup526, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)ik(z?)$")>;
def SPRWriteResGroup527 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 13;
let NumMicroOps = 3;
}
@@ -4828,7 +4828,7 @@ def : InstRW<[SPRWriteResGroup527], (instregex "^VREDUCEPHZ(128|256)rri$",
"^VREDUCESHZrri(b?)$")>;
def SPRWriteResGroup528 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 16;
let NumMicroOps = 3;
}
@@ -4837,28 +4837,28 @@ def : InstRW<[SPRWriteResGroup528], (instregex "^VREDUCEPHZ(128|256)rrik(z?)$",
"^VREDUCESHZrri(k|bkz)$")>;
def SPRWriteResGroup529 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 20;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup529, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)i$")>;
def SPRWriteResGroup530 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let Latency = 22;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup530, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)ik(z?)$")>;
def SPRWriteResGroup531 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 13;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup531], (instregex "^VREDUCEPHZrri(b?)$")>;
def SPRWriteResGroup532 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let Latency = 16;
let NumMicroOps = 3;
}
@@ -4866,7 +4866,7 @@ def : InstRW<[SPRWriteResGroup532], (instregex "^VREDUCEPHZrri(bk|kz)$",
"^VREDUCEPHZrri(k|bkz)$")>;
def SPRWriteResGroup533 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 8;
let NumMicroOps = 2;
}
@@ -4874,7 +4874,7 @@ def : InstRW<[SPRWriteResGroup533], (instregex "^VRNDSCALEP(D|S)Zrri((b|k|bk|kz)
"^VRNDSCALEP(D|S)Zrribkz$")>;
def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 17;
let NumMicroOps = 3;
}
@@ -4888,7 +4888,7 @@ def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ25
def : InstRW<[SPRWriteResGroup534, ReadAfterVecLd], (instregex "^VSCALEFSHZrmk(z?)$")>;
def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 11;
let NumMicroOps = 2;
}
@@ -4899,7 +4899,7 @@ def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$"
"^VSCALEFSHZrrk(z?)$")>;
def SPRWriteResGroup536 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 17;
let NumMicroOps = 3;
}
@@ -4908,7 +4908,7 @@ def : InstRW<[SPRWriteResGroup536, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZrm
"^VSCALEFPHZrm(k|bkz)$")>;
def SPRWriteResGroup537 : SchedWriteRes<[SPRPort00]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 11;
let NumMicroOps = 2;
}
@@ -4918,7 +4918,7 @@ def : InstRW<[SPRWriteResGroup537], (instregex "^VRNDSCALEPHZrri(bk|kz)$",
"^VSCALEFPHZrr(k|bkz)$")>;
def SPRWriteResGroup538 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
@@ -4942,28 +4942,28 @@ def : InstRW<[SPRWriteResGroup540, ReadAfterVecXLd], (instregex "^VSQRTPDZ128m(b
def : InstRW<[SPRWriteResGroup540, ReadAfterVecLd], (instregex "^VSQRTSDZm_Intk(z?)$")>;
def SPRWriteResGroup541 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 38;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup541, ReadAfterVecYLd], (instrs VSQRTPDZm)>;
def SPRWriteResGroup542 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 39;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup542, ReadAfterVecYLd], (instrs VSQRTPDZmb)>;
def SPRWriteResGroup543 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 31;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup543], (instrs VSQRTPDZr)>;
def SPRWriteResGroup544 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 41;
let NumMicroOps = 4;
}
@@ -4971,7 +4971,7 @@ def : InstRW<[SPRWriteResGroup544, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b
"^VSQRTPHZ128m(k|bkz)$")>;
def SPRWriteResGroup545 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 35;
let NumMicroOps = 3;
}
@@ -4979,21 +4979,21 @@ def : InstRW<[SPRWriteResGroup545], (instregex "^VSQRTPHZ(128|256)rk$")>;
def : InstRW<[SPRWriteResGroup545], (instrs VSQRTPHZ256rkz)>;
def SPRWriteResGroup546 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 12;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup546], (instrs VSQRTPHZ128rkz)>;
def SPRWriteResGroup547 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 40;
let NumMicroOps = 4;
}
def : InstRW<[SPRWriteResGroup547, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b?)$")>;
def SPRWriteResGroup548 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1, 1];
+ let ResourceCycles = [2, 1, 1];
let Latency = 42;
let NumMicroOps = 4;
}
@@ -5001,14 +5001,14 @@ def : InstRW<[SPRWriteResGroup548, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b
"^VSQRTPHZ256m(k|bkz)$")>;
def SPRWriteResGroup549 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1];
let Latency = 53;
let NumMicroOps = 9;
}
def : InstRW<[SPRWriteResGroup549, ReadAfterVecYLd], (instregex "^VSQRTPHZm(b?)$")>;
def SPRWriteResGroup550 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
- let ReleaseAtCycles = [4, 2, 1, 1, 1];
+ let ResourceCycles = [4, 2, 1, 1, 1];
let Latency = 55;
let NumMicroOps = 9;
}
@@ -5016,14 +5016,14 @@ def : InstRW<[SPRWriteResGroup550, ReadAfterVecYLd], (instregex "^VSQRTPHZm(bk|k
"^VSQRTPHZm(k|bkz)$")>;
def SPRWriteResGroup551 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let Latency = 45;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup551], (instregex "^VSQRTPHZr(b?)$")>;
def SPRWriteResGroup552 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let Latency = 47;
let NumMicroOps = 6;
}
@@ -5031,98 +5031,98 @@ def : InstRW<[SPRWriteResGroup552], (instregex "^VSQRTPHZr(bk|kz)$",
"^VSQRTPHZr(k|bkz)$")>;
def SPRWriteResGroup553 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 19;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup553], (instrs VSQRTPSZr)>;
def SPRWriteResGroup554 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10]> {
- let ReleaseAtCycles = [1, 2, 3, 3, 1];
+ let ResourceCycles = [1, 2, 3, 3, 1];
let Latency = 12;
let NumMicroOps = 10;
}
def : InstRW<[SPRWriteResGroup554], (instrs VZEROALL)>;
def SPRWriteResGroup555 : SchedWriteRes<[SPRPort00_01_05_06]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup555], (instrs WAIT)>;
def SPRWriteResGroup556 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+ let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 144;
}
def : InstRW<[SPRWriteResGroup556], (instrs WRMSR)>;
def SPRWriteResGroup557 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
- let ReleaseAtCycles = [2, 1, 4, 1];
+ let ResourceCycles = [2, 1, 4, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 8;
}
def : InstRW<[SPRWriteResGroup557], (instrs WRPKRUr)>;
def SPRWriteResGroup558 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup558, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
def SPRWriteResGroup559 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup559, WriteRMW], (instrs XADD8rm)>;
def SPRWriteResGroup560 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
- let ReleaseAtCycles = [4, 1];
+ let ResourceCycles = [4, 1];
let Latency = 39;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup560, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
def SPRWriteResGroup561 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
- let ReleaseAtCycles = [5, 1];
+ let ResourceCycles = [5, 1];
let Latency = 39;
let NumMicroOps = 6;
}
def : InstRW<[SPRWriteResGroup561, WriteRMW], (instrs XCHG64rm)>;
def SPRWriteResGroup562 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
- let ReleaseAtCycles = [4, 1];
+ let ResourceCycles = [4, 1];
let Latency = 40;
let NumMicroOps = 5;
}
def : InstRW<[SPRWriteResGroup562, WriteRMW], (instrs XCHG8rm)>;
def SPRWriteResGroup563 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_05, SPRPort01, SPRPort05, SPRPort06]> {
- let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
+ let ResourceCycles = [2, 4, 2, 1, 2, 4];
let Latency = 17;
let NumMicroOps = 15;
}
def : InstRW<[SPRWriteResGroup563], (instrs XCH_F)>;
def SPRWriteResGroup564 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01]> {
- let ReleaseAtCycles = [7, 3, 8, 5];
+ let ResourceCycles = [7, 3, 8, 5];
let Latency = 4;
let NumMicroOps = 23;
}
def : InstRW<[SPRWriteResGroup564], (instrs XGETBV)>;
def SPRWriteResGroup565 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = 7;
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup565], (instrs XLAT)>;
def SPRWriteResGroup566 : SchedWriteRes<[SPRPort01, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
- let ReleaseAtCycles = [1, 21, 1, 8];
+ let ResourceCycles = [1, 21, 1, 8];
let Latency = 37;
let NumMicroOps = 31;
}
@@ -5130,70 +5130,70 @@ def : InstRW<[SPRWriteResGroup566], (instregex "^XRSTOR((S|64)?)$")>;
def : InstRW<[SPRWriteResGroup566], (instrs XRSTORS64)>;
def SPRWriteResGroup567 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 42;
let NumMicroOps = 140;
}
def : InstRW<[SPRWriteResGroup567], (instrs XSAVE)>;
def SPRWriteResGroup568 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 41;
let NumMicroOps = 140;
}
def : InstRW<[SPRWriteResGroup568], (instrs XSAVE64)>;
def SPRWriteResGroup569 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+ let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 151;
}
def : InstRW<[SPRWriteResGroup569], (instrs XSAVEC)>;
def SPRWriteResGroup570 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+ let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 152;
}
def : InstRW<[SPRWriteResGroup570], (instrs XSAVEC64)>;
def SPRWriteResGroup571 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+ let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
let Latency = 42;
let NumMicroOps = 155;
}
def : InstRW<[SPRWriteResGroup571], (instrs XSAVEOPT)>;
def SPRWriteResGroup572 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+ let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
let Latency = 42;
let NumMicroOps = 156;
}
def : InstRW<[SPRWriteResGroup572], (instrs XSAVEOPT64)>;
def SPRWriteResGroup573 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+ let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
let Latency = 42;
let NumMicroOps = 184;
}
def : InstRW<[SPRWriteResGroup573], (instrs XSAVES)>;
def SPRWriteResGroup574 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
- let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+ let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
let Latency = 42;
let NumMicroOps = 186;
}
def : InstRW<[SPRWriteResGroup574], (instrs XSAVES64)>;
def SPRWriteResGroup575 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
- let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
+ let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
let Latency = 5;
let NumMicroOps = 54;
}
def : InstRW<[SPRWriteResGroup575], (instrs XSETBV)>;
def SPRWriteResGroup576 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let Latency = SapphireRapidsModel.MaxLatency;
let NumMicroOps = 3;
}
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 92ed491bc29613..9412a40be48cf9 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -94,7 +94,7 @@ multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -102,7 +102,7 @@ multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -424,7 +424,7 @@ defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
def : WriteRes<WriteVecInsert, [SKLPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
let Latency = 6;
@@ -494,48 +494,48 @@ defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
let Latency = 25;
let NumMicroOps = 10;
- let ReleaseAtCycles = [4,3,1,1,1];
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4,3,1];
+ let ResourceCycles = [4,3,1];
}
def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
let Latency = 24;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
// MOVMSK Instructions.
@@ -548,46 +548,46 @@ def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; }
def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
let Latency = 20;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,2];
+ let ResourceCycles = [3,6,2];
}
def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
let Latency = 25;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,1,1];
+ let ResourceCycles = [3,6,1,1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SKLPort5]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
// Catch-all for expensive system instructions.
@@ -607,8 +607,8 @@ def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def Wri
def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
// Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -628,7 +628,7 @@ defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
"MMX_PADDUS(B|W)rr",
@@ -643,7 +643,7 @@ def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
"UCOM_F(P?)r")>;
@@ -651,35 +651,35 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
"VPBLENDD(Y?)rri")>;
@@ -687,7 +687,7 @@ def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,
SIDT64m,
@@ -698,7 +698,7 @@ def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,
def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
let Latency = 1;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
@@ -706,14 +706,14 @@ def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
MMX_MOVDQ2Qrr)>;
@@ -721,7 +721,7 @@ def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
WAIT,
@@ -730,21 +730,21 @@ def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup23], (instrs CWD,
JCXZ, JECXZ, JRCXZ,
@@ -756,21 +756,21 @@ def: InstRW<[SKLWriteResGroup23], (instrs CWD,
def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
STOSB, STOSL, STOSQ, STOSW)>;
@@ -779,7 +779,7 @@ def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
"PEXT(32|64)rr")>;
@@ -787,7 +787,7 @@ def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
"VPBROADCAST(B|W)rr")>;
@@ -795,21 +795,21 @@ def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0
def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
"(V?)PHSUBSW(Y?)rr")>;
@@ -817,7 +817,7 @@ def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -826,21 +826,21 @@ def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -848,49 +848,49 @@ def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 5;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
"IST_F(16|32)m")>;
@@ -898,63 +898,63 @@ def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
def SKLWriteResGroup56 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>;
def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,4];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
VPBROADCASTDrm,
@@ -966,14 +966,14 @@ def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
MMX_PADDSWrm,
@@ -999,7 +999,7 @@ def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
@@ -1007,7 +1007,7 @@ def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
"MOVBE(16|32|64)rm")>;
@@ -1015,7 +1015,7 @@ def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
@@ -1023,21 +1023,21 @@ def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -1046,7 +1046,7 @@ def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
@@ -1054,14 +1054,14 @@ def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,5];
+ let ResourceCycles = [1,5];
}
def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
@@ -1077,7 +1077,7 @@ def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
"(V?)PMOV(SX|ZX)BQrm",
@@ -1089,7 +1089,7 @@ def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
VINSERTI128rm,
@@ -1101,7 +1101,7 @@ def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
MMX_PACKSSWBrm,
@@ -1110,7 +1110,7 @@ def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
@@ -1118,28 +1118,28 @@ def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -1147,7 +1147,7 @@ def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
@@ -1155,14 +1155,14 @@ def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,1,1];
+ let ResourceCycles = [1,1,1,1,1];
}
def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
@@ -1170,14 +1170,14 @@ def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,3,1,2];
+ let ResourceCycles = [1,3,1,2];
}
def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
"PEXT(32|64)rm")>;
@@ -1185,7 +1185,7 @@ def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
@@ -1197,7 +1197,7 @@ def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
@@ -1207,14 +1207,14 @@ def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 8;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
"RCR(8|16|32|64)m(1|i)")>;
@@ -1222,7 +1222,7 @@ def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,3];
+ let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@@ -1233,21 +1233,21 @@ def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,2,1];
}
def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
VPCMPGTQrm,
@@ -1259,14 +1259,14 @@ def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>;
def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
"(V?)PHSUBSWrm")>;
@@ -1274,7 +1274,7 @@ def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
"LSL(16|32|64)rm")>;
@@ -1282,7 +1282,7 @@ def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
@@ -1291,14 +1291,14 @@ def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 10;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
VPHSUBSWYrm)>;
@@ -1306,28 +1306,28 @@ def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 10;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,3];
+ let ResourceCycles = [1,1,1,1,1,3];
}
def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,3,2];
+ let ResourceCycles = [2,3,2];
}
def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
"RCR(16|32|64)rCL")>;
@@ -1335,119 +1335,119 @@ def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,5,1,2];
+ let ResourceCycles = [1,5,1,2];
}
def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,9];
+ let ResourceCycles = [2,9];
}
def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
- let ReleaseAtCycles = [2,4,1,3];
+ let ResourceCycles = [2,4,1,3];
}
def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
let Latency = 15;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 15;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,1,1,5,1,1];
+ let ResourceCycles = [1,1,1,5,1,1];
}
def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,1,1,4,2,5];
+ let ResourceCycles = [1,1,1,4,2,5];
}
def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
let Latency = 16;
let NumMicroOps = 16;
- let ReleaseAtCycles = [16];
+ let ResourceCycles = [16];
}
def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
let Latency = 17;
let NumMicroOps = 15;
- let ReleaseAtCycles = [2,1,2,4,2,4];
+ let ResourceCycles = [2,1,2,4,2,4];
}
def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,5];
+ let ResourceCycles = [1,1,1,5];
}
def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,1,1,4,1,2];
+ let ResourceCycles = [2,1,1,4,1,2];
}
def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
let Latency = 20;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 20;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,1,2];
+ let ResourceCycles = [1,1,1,1,1,1,2];
}
def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
let Latency = 20;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,2,7];
+ let ResourceCycles = [1,2,7];
}
def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 22;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
let Latency = 18;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
VGATHERQPDrm, VPGATHERQQrm,
@@ -1456,7 +1456,7 @@ def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
let Latency = 20;
let NumMicroOps = 5; // 2 uops peform multiple loads
- let ReleaseAtCycles = [1,4,1,1];
+ let ResourceCycles = [1,4,1,1];
}
def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
VGATHERDPSrm, VPGATHERDDrm,
@@ -1466,42 +1466,42 @@ def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
let Latency = 22;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,8,1,1];
+ let ResourceCycles = [1,8,1,1];
}
def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
- let ReleaseAtCycles = [2,1,4,1,1,4,6];
+ let ResourceCycles = [2,1,4,1,1,4,6];
}
def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 25;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 27;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 30;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,3,4,10];
+ let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
"IN(8|16|32)rr")>;
@@ -1509,7 +1509,7 @@ def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,2,1,4,10];
+ let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
@@ -1517,35 +1517,35 @@ def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 37;
let NumMicroOps = 31;
- let ReleaseAtCycles = [1,8,1,21];
+ let ResourceCycles = [1,8,1,21];
}
def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
let Latency = 40;
let NumMicroOps = 18;
- let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
+ let ResourceCycles = [1,1,2,3,1,1,1,8];
}
def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 41;
let NumMicroOps = 39;
- let ReleaseAtCycles = [1,10,1,1,26];
+ let ResourceCycles = [1,10,1,1,26];
}
def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
let Latency = 42;
let NumMicroOps = 22;
- let ReleaseAtCycles = [2,20];
+ let ResourceCycles = [2,20];
}
def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 42;
let NumMicroOps = 40;
- let ReleaseAtCycles = [1,11,1,1,26];
+ let ResourceCycles = [1,11,1,1,26];
}
def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
@@ -1553,42 +1553,42 @@ def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 46;
let NumMicroOps = 44;
- let ReleaseAtCycles = [1,11,1,1,30];
+ let ResourceCycles = [1,11,1,1,30];
}
def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
let Latency = 62;
let NumMicroOps = 64;
- let ReleaseAtCycles = [2,8,5,10,39];
+ let ResourceCycles = [2,8,5,10,39];
}
def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 63;
let NumMicroOps = 88;
- let ReleaseAtCycles = [4,4,31,1,2,1,45];
+ let ResourceCycles = [4,4,31,1,2,1,45];
}
def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 63;
let NumMicroOps = 90;
- let ReleaseAtCycles = [4,2,33,1,2,1,47];
+ let ResourceCycles = [4,2,33,1,2,1,47];
}
def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
- let ReleaseAtCycles = [6,3,6];
+ let ResourceCycles = [6,3,6];
}
def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 106;
let NumMicroOps = 100;
- let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
+ let ResourceCycles = [9,1,11,16,1,11,21,30];
}
def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
@@ -1658,7 +1658,7 @@ def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
@@ -1677,7 +1677,7 @@ def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -1691,13 +1691,13 @@ def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
// CMOVs that use both Z and C flag require an extra uop.
def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
let Latency = 7;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
let NumMicroOps = 3;
}
@@ -1717,13 +1717,13 @@ def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index ed22f95c83e582..2f9d075891f87f 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -94,7 +94,7 @@ multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -102,7 +102,7 @@ multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -425,7 +425,7 @@ defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
def : WriteRes<WriteVecInsert, [SKXPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
let Latency = 6;
@@ -490,48 +490,48 @@ defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8
def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
let Latency = 19;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
let Latency = 25;
let NumMicroOps = 10;
- let ReleaseAtCycles = [4,3,1,1,1];
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
let Latency = 16;
let NumMicroOps = 4;
- let ReleaseAtCycles = [3,1];
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [4,3,1];
+ let ResourceCycles = [4,3,1];
}
def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
let Latency = 24;
let NumMicroOps = 9;
- let ReleaseAtCycles = [4,3,1,1];
+ let ResourceCycles = [4,3,1,1];
}
// MOVMSK Instructions.
@@ -544,46 +544,46 @@ def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
let Latency = 20;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,2];
+ let ResourceCycles = [3,6,2];
}
def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 25;
let NumMicroOps = 11;
- let ReleaseAtCycles = [3,6,1,1];
+ let ResourceCycles = [3,6,1,1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SKXPort5]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
// Catch-all for expensive system instructions.
@@ -603,8 +603,8 @@ def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def Wri
def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
// Load/store MXCSR.
-def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
-def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
+def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -624,7 +624,7 @@ defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
"KANDN(B|D|Q|W)rr",
@@ -652,7 +652,7 @@ def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
"KMOV(B|D|Q|W)kr",
@@ -661,35 +661,35 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
"VBLENDMPS(Z128|Z256)rr",
@@ -707,7 +707,7 @@ def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup10], (instrs SGDT64m,
SIDT64m,
@@ -718,7 +718,7 @@ def: InstRW<[SKXWriteResGroup10], (instrs SGDT64m,
def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
let Latency = 1;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
@@ -727,14 +727,14 @@ def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
MMX_MOVDQ2Qrr)>;
@@ -742,7 +742,7 @@ def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
WAIT,
@@ -751,21 +751,21 @@ def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup23], (instrs CWD,
JCXZ, JECXZ, JRCXZ,
@@ -777,21 +777,21 @@ def: InstRW<[SKXWriteResGroup23], (instrs CWD,
def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
STOSB, STOSL, STOSQ, STOSW)>;
@@ -800,14 +800,14 @@ def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
let Latency = 2;
let NumMicroOps = 5;
- let ReleaseAtCycles = [2,2,1];
+ let ResourceCycles = [2,2,1];
}
def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
"KORTEST(B|D|Q|W)rr",
@@ -816,7 +816,7 @@ def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
"PEXT(32|64)rr")>;
@@ -824,7 +824,7 @@ def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
"VALIGND(Z|Z128|Z256)rri",
@@ -835,7 +835,7 @@ def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0
def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
"KSHIFTL(B|D|Q|W)ri",
@@ -858,28 +858,28 @@ def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,
MMX_PACKSSWBrr,
@@ -888,21 +888,21 @@ def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,
def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@@ -910,49 +910,49 @@ def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
let Latency = 5;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 8;
- let ReleaseAtCycles = [2,4,2];
+ let ResourceCycles = [2,4,2];
}
def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
let Latency = 3;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
"VCVTPD2UQQ(Z128|Z256)rr",
@@ -968,7 +968,7 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
let Latency = 4;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,
VCVTPD2UQQZrr,
@@ -982,7 +982,7 @@ def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,
def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
"VEXPANDPS(Z|Z128|Z256)rr",
@@ -1008,7 +1008,7 @@ def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 4;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
"IST_F(16|32)m",
@@ -1017,28 +1017,28 @@ def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
def SKXWriteResGroup56 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 4;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
}
def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
}
def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
"MMX_CVT(T?)PS2PIrr",
@@ -1069,21 +1069,21 @@ def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort01]> {
let Latency = 5;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
"VCVTPS2PHZ256mr(b?)",
@@ -1092,7 +1092,7 @@ def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 5;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
"VPMOVDW(Z|Z128|Z256)mr(b?)",
@@ -1115,21 +1115,21 @@ def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,4];
+ let ResourceCycles = [1,4];
}
def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 5;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,4];
+ let ResourceCycles = [1,1,4];
}
def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
let Latency = 6;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
VPBROADCASTDrm,
@@ -1141,7 +1141,7 @@ def: InstRW<[SKXWriteResGroup71], (instregex "(V?)MOVSHDUPrm",
def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
@@ -1153,7 +1153,7 @@ def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
MMX_PADDSWrm,
@@ -1179,7 +1179,7 @@ def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;
def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
@@ -1187,7 +1187,7 @@ def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
"MOVBE(16|32|64)rm")>;
@@ -1195,7 +1195,7 @@ def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
@@ -1203,7 +1203,7 @@ def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
@@ -1211,7 +1211,7 @@ def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 6;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
"VCVTSI642SSZrr",
@@ -1220,14 +1220,14 @@ def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@@ -1236,7 +1236,7 @@ def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,1,1,1];
+ let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
"PUSH(16|32|64)rmm")>;
@@ -1244,14 +1244,14 @@ def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,5];
+ let ResourceCycles = [1,5];
}
def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
let Latency = 7;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
@@ -1267,14 +1267,14 @@ def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
"VMOVSSZrm(b?)")>;
@@ -1282,7 +1282,7 @@ def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
"(V?)PMOV(SX|ZX)BQrm",
@@ -1294,7 +1294,7 @@ def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
"VCVTPD2DQ(Y|Z256)rr",
@@ -1313,7 +1313,7 @@ def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
VCVTPD2DQZrr,
@@ -1332,7 +1332,7 @@ def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 7;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
VPBLENDDrmi)>;
@@ -1368,7 +1368,7 @@ def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,
MMX_PACKSSWBrm,
@@ -1377,7 +1377,7 @@ def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,
def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
"VPERMI2W256rr",
@@ -1389,7 +1389,7 @@ def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
@@ -1397,7 +1397,7 @@ def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort01]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
"VCVT(T?)SS2USI64Zrr")>;
@@ -1405,28 +1405,28 @@ def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;
def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 7;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
"VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
@@ -1436,7 +1436,7 @@ def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@@ -1444,7 +1444,7 @@ def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
@@ -1452,14 +1452,14 @@ def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,1,1];
+ let ResourceCycles = [1,1,1,1,1];
}
def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
@@ -1467,7 +1467,7 @@ def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,2,2,2];
+ let ResourceCycles = [1,2,2,2];
}
def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
VPSCATTERQQZ128mr,
@@ -1477,14 +1477,14 @@ def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
- let ReleaseAtCycles = [1,3,1,2];
+ let ResourceCycles = [1,3,1,2];
}
def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 11;
- let ReleaseAtCycles = [1,4,4,2];
+ let ResourceCycles = [1,4,4,2];
}
def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
VPSCATTERQQZ256mr,
@@ -1494,7 +1494,7 @@ def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 19;
- let ReleaseAtCycles = [1,8,8,2];
+ let ResourceCycles = [1,8,8,2];
}
def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
VPSCATTERQQZmr,
@@ -1504,14 +1504,14 @@ def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 36;
- let ReleaseAtCycles = [1,16,1,16,2];
+ let ResourceCycles = [1,16,1,16,2];
}
def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
"PEXT(32|64)rm")>;
@@ -1519,7 +1519,7 @@ def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
"VPBROADCASTB(Z|Z256)rm(b?)",
@@ -1533,7 +1533,7 @@ def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
VPBLENDDYrmi)>;
@@ -1592,14 +1592,14 @@ def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 8;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,2,1];
+ let ResourceCycles = [1,2,1];
}
def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,1,1,2];
+ let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
"RCR(8|16|32|64)m(1|i)")>;
@@ -1607,7 +1607,7 @@ def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,3];
+ let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@@ -1618,14 +1618,14 @@ def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
- let ReleaseAtCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,2,1];
}
def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,2,1,2,2];
+ let ResourceCycles = [1,2,1,2,2];
}
def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
VPSCATTERQDZ256mr,
@@ -1635,7 +1635,7 @@ def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 12;
- let ReleaseAtCycles = [1,4,1,4,2];
+ let ResourceCycles = [1,4,1,4,2];
}
def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
VSCATTERDPSZ128mr)>;
@@ -1643,7 +1643,7 @@ def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 20;
- let ReleaseAtCycles = [1,8,1,8,2];
+ let ResourceCycles = [1,8,1,8,2];
}
def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
VSCATTERDPSZ256mr)>;
@@ -1651,21 +1651,21 @@ def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 36;
- let ReleaseAtCycles = [1,16,1,16,2];
+ let ResourceCycles = [1,16,1,16,2];
}
def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
VPMOVSXDQYrm,
@@ -1691,7 +1691,7 @@ def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
"VCMP(SD|SS)Zrm",
@@ -1716,7 +1716,7 @@ def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort01]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
"(V?)CVTPS2PDrm")>;
@@ -1724,7 +1724,7 @@ def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
let Latency = 9;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
"(V?)PHSUBSWrm")>;
@@ -1732,7 +1732,7 @@ def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
"LSL(16|32|64)rm")>;
@@ -1740,7 +1740,7 @@ def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
@@ -1755,7 +1755,7 @@ def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
"VCMPPS(Z|Z256)rm(b?)i",
@@ -1783,7 +1783,7 @@ def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort01]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
"VCVTDQ2PSZ128rm(b?)",
@@ -1816,7 +1816,7 @@ def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 10;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
"VEXPANDPSZ128rm(b?)",
@@ -1826,7 +1826,7 @@ def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
let Latency = 10;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
VPHSUBSWYrm)>;
@@ -1834,21 +1834,21 @@ def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 10;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,3];
+ let ResourceCycles = [1,1,1,1,1,3];
}
def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort01]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
VCVTPS2PDYrm)>;
@@ -1871,7 +1871,7 @@ def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
"VEXPANDPD(Z|Z256)rm(b?)",
@@ -1882,14 +1882,14 @@ def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
let Latency = 11;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2DQrm,
CVTTPD2DQrm,
@@ -1899,14 +1899,14 @@ def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2DQrm,
def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 11;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
- let ReleaseAtCycles = [2,3,2];
+ let ResourceCycles = [2,3,2];
}
def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
"RCR(16|32|64)rCL")>;
@@ -1914,42 +1914,42 @@ def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
- let ReleaseAtCycles = [1,5,1,2];
+ let ResourceCycles = [1,5,1,2];
}
def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,9];
+ let ResourceCycles = [2,9];
}
def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
let Latency = 15;
let NumMicroOps = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort01]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
"VCVT(T?)SS2USI64Zrm(b?)")>;
@@ -1957,7 +1957,7 @@ def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
let Latency = 12;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
"VCVT(T?)PS2UQQZrm(b?)")>;
@@ -1965,7 +1965,7 @@ def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
"VPERMWZ256rm(b?)",
@@ -1974,14 +1974,14 @@ def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 13;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
"VPERMT2W128rm(b?)")>;
@@ -1989,14 +1989,14 @@ def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort01]> {
let Latency = 14;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
"VCVTPD2UDQZrm(b?)",
@@ -2008,7 +2008,7 @@ def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 14;
let NumMicroOps = 4;
- let ReleaseAtCycles = [2,1,1];
+ let ResourceCycles = [2,1,1];
}
def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
"VPERMI2Wrm(b?)",
@@ -2018,98 +2018,98 @@ def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
- let ReleaseAtCycles = [2,4,1,3];
+ let ResourceCycles = [2,4,1,3];
}
def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
let Latency = 15;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
let Latency = 15;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,2,2,1,2];
+ let ResourceCycles = [1,2,2,1,2];
}
def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 15;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,1,1,5,1,1];
+ let ResourceCycles = [1,1,1,5,1,1];
}
def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
- let ReleaseAtCycles = [1,1,1,4,2,5];
+ let ResourceCycles = [1,1,1,4,2,5];
}
def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
let Latency = 12;
let NumMicroOps = 34;
- let ReleaseAtCycles = [1, 4, 5];
+ let ResourceCycles = [1, 4, 5];
}
def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
let Latency = 17;
let NumMicroOps = 15;
- let ReleaseAtCycles = [2,1,2,4,2,4];
+ let ResourceCycles = [2,1,2,4,2,4];
}
def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {
let Latency = 21;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,5];
+ let ResourceCycles = [1,1,1,5];
}
def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 18;
let NumMicroOps = 11;
- let ReleaseAtCycles = [2,1,1,4,1,2];
+ let ResourceCycles = [2,1,1,4,1,2];
}
def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {
let Latency = 22;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {
let Latency = 22;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
let Latency = 20;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 17;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
VGATHERDPDZ128rm, VPGATHERDQZ128rm,
@@ -2118,7 +2118,7 @@ def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 19;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,4,1,1];
+ let ResourceCycles = [1,4,1,1];
}
def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
VGATHERQPDZ256rm, VPGATHERQQZ256rm,
@@ -2128,7 +2128,7 @@ def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 21;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,8,1,1];
+ let ResourceCycles = [1,8,1,1];
}
def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
VGATHERDPDZrm, VPGATHERDQZrm,
@@ -2138,35 +2138,35 @@ def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 25;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,16,1,1];
+ let ResourceCycles = [1,16,1,1];
}
def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 20;
let NumMicroOps = 8;
- let ReleaseAtCycles = [1,1,1,1,1,1,2];
+ let ResourceCycles = [1,1,1,1,1,1,2];
}
def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
let Latency = 20;
let NumMicroOps = 10;
- let ReleaseAtCycles = [1,2,7];
+ let ResourceCycles = [1,2,7];
}
def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 22;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
let Latency = 18;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,2,1,1];
+ let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
VGATHERQPDrm, VPGATHERQQrm,
@@ -2175,7 +2175,7 @@ def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
let Latency = 20;
let NumMicroOps = 5; // 2 uops peform multiple loads
- let ReleaseAtCycles = [1,4,1,1];
+ let ResourceCycles = [1,4,1,1];
}
def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
VGATHERDPSrm, VPGATHERDDrm,
@@ -2185,14 +2185,14 @@ def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
let Latency = 22;
let NumMicroOps = 5; // 2 uops perform multiple loads
- let ReleaseAtCycles = [1,8,1,1];
+ let ResourceCycles = [1,8,1,1];
}
def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
let Latency = 22;
let NumMicroOps = 14;
- let ReleaseAtCycles = [5,5,4];
+ let ResourceCycles = [5,5,4];
}
def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
"VPCONFLICTQZ256rr")>;
@@ -2200,42 +2200,42 @@ def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
- let ReleaseAtCycles = [2,1,4,1,1,4,6];
+ let ResourceCycles = [2,1,4,1,1,4,6];
}
def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 25;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 27;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,1];
+ let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
let Latency = 29;
let NumMicroOps = 15;
- let ReleaseAtCycles = [5,5,1,4];
+ let ResourceCycles = [5,5,1,4];
}
def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 30;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,3,4,10];
+ let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
"IN(8|16|32)rr")>;
@@ -2243,7 +2243,7 @@ def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
- let ReleaseAtCycles = [1,5,2,1,4,10];
+ let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
"OUT(8|16|32)rr")>;
@@ -2251,7 +2251,7 @@ def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
let Latency = 37;
let NumMicroOps = 21;
- let ReleaseAtCycles = [9,7,5];
+ let ResourceCycles = [9,7,5];
}
def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
"VPCONFLICTQZrr")>;
@@ -2259,35 +2259,35 @@ def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
let Latency = 37;
let NumMicroOps = 31;
- let ReleaseAtCycles = [1,8,1,21];
+ let ResourceCycles = [1,8,1,21];
}
def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
let Latency = 40;
let NumMicroOps = 18;
- let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
+ let ResourceCycles = [1,1,2,3,1,1,1,8];
}
def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 41;
let NumMicroOps = 39;
- let ReleaseAtCycles = [1,10,1,1,26];
+ let ResourceCycles = [1,10,1,1,26];
}
def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
let Latency = 42;
let NumMicroOps = 22;
- let ReleaseAtCycles = [2,20];
+ let ResourceCycles = [2,20];
}
def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 42;
let NumMicroOps = 40;
- let ReleaseAtCycles = [1,11,1,1,26];
+ let ResourceCycles = [1,11,1,1,26];
}
def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
@@ -2295,7 +2295,7 @@ def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
let Latency = 44;
let NumMicroOps = 22;
- let ReleaseAtCycles = [9,7,1,5];
+ let ResourceCycles = [9,7,1,5];
}
def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
"VPCONFLICTQZrm(b?)")>;
@@ -2303,56 +2303,56 @@ def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
let Latency = 62;
let NumMicroOps = 64;
- let ReleaseAtCycles = [2,8,5,10,39];
+ let ResourceCycles = [2,8,5,10,39];
}
def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 63;
let NumMicroOps = 88;
- let ReleaseAtCycles = [4,4,31,1,2,1,45];
+ let ResourceCycles = [4,4,31,1,2,1,45];
}
def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 63;
let NumMicroOps = 90;
- let ReleaseAtCycles = [4,2,33,1,2,1,47];
+ let ResourceCycles = [4,2,33,1,2,1,47];
}
def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
let Latency = 67;
let NumMicroOps = 35;
- let ReleaseAtCycles = [17,11,7];
+ let ResourceCycles = [17,11,7];
}
def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
let Latency = 74;
let NumMicroOps = 36;
- let ReleaseAtCycles = [17,11,1,7];
+ let ResourceCycles = [17,11,1,7];
}
def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
- let ReleaseAtCycles = [6,3,6];
+ let ResourceCycles = [6,3,6];
}
def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 106;
let NumMicroOps = 100;
- let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
+ let ResourceCycles = [9,1,11,16,1,11,21,30];
}
def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 140;
let NumMicroOps = 4;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
@@ -2439,7 +2439,7 @@ def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
let Latency = 1;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
@@ -2462,7 +2462,7 @@ def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
let Latency = 3;
let NumMicroOps = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@@ -2476,13 +2476,13 @@ def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
// CMOVs that use both Z and C flag require an extra uop.
def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
let Latency = 7;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
let NumMicroOps = 3;
}
@@ -2502,13 +2502,13 @@ def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
let Latency = 3;
- let ReleaseAtCycles = [1,1,2];
+ let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index faa8be05d179c4..3321ed737a4448 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -27,13 +27,13 @@ def ReadInt2Fpu : SchedRead;
// load + WriteRMW.
def WriteRMW : SchedWrite;
-// Helper to set SchedWrite ExePorts/Latency/ReleaseAtCycles/NumMicroOps.
+// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
multiclass X86WriteRes<SchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
int Lat, list<int> Res, int UOps> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index c92bc97cfb385a..b7336161b2e061 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -62,14 +62,14 @@ multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant.
def : WriteRes<SchedRW, RRPorts> {
let Latency = RRLat;
- let ReleaseAtCycles = RRRes;
+ let ResourceCycles = RRRes;
let NumMicroOps = RRUOps;
}
// Memory variant.
def : WriteRes<SchedRW.Folded, RMPorts> {
let Latency = RMLat;
- let ReleaseAtCycles = RMRes;
+ let ResourceCycles = RMRes;
let NumMicroOps = RMUOps;
}
}
@@ -122,11 +122,11 @@ defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move
def : WriteRes<WriteSETCC, [AtomPort01]>;
def : WriteRes<WriteSETCCStore, [AtomPort01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
@@ -462,10 +462,10 @@ defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
// MOVMSK Instructions.
////////////////////////////////////////////////////////////////////////////////
-def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
-def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
+def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
+def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
-def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
+def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
////////////////////////////////////////////////////////////////////////////////
// AES instructions.
@@ -505,7 +505,7 @@ defm : X86WriteRes<WriteSTMXCSR, [AtomPort0,AtomPort1], 15, [15,15], 4>;
// Port0
def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr,
MOVSX64rr32)>;
@@ -517,14 +517,14 @@ def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|6
// Port1
def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;
def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
let Latency = 5;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
}
def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>;
@@ -532,7 +532,7 @@ def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
// Port0 and Port1
def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
}
def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
POP16rmr, POP32rmr, POP64rmr,
@@ -546,41 +546,41 @@ def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
let Latency = 5;
- let ReleaseAtCycles = [5, 5];
+ let ResourceCycles = [5, 5];
}
def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>;
def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
def AtomWrite0_1_7 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 7;
- let ReleaseAtCycles = [6,6];
+ let ResourceCycles = [6,6];
}
def : InstRW<[AtomWrite0_1_7], (instregex "CVTSI642SDrm(_Int)?")>;
def AtomWrite0_1_7_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 7;
- let ReleaseAtCycles = [8,8];
+ let ResourceCycles = [8,8];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrr(_Int)?")>;
def AtomWrite0_1_8_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 8;
- let ReleaseAtCycles = [8,8];
+ let ResourceCycles = [8,8];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrm(_Int)?")>;
def AtomWrite0_1_9 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 9;
- let ReleaseAtCycles = [9,9];
+ let ResourceCycles = [9,9];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_9], (instregex "CVT(T)?SS2SI64rr(_Int)?")>;
def AtomWrite0_1_10 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 10;
- let ReleaseAtCycles = [11,11];
+ let ResourceCycles = [11,11];
let NumMicroOps = 5;
}
def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;
@@ -588,7 +588,7 @@ def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;
// Port0 or Port1
def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
LFENCE,
@@ -597,7 +597,7 @@ def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
PUSH16rmm, PUSH32rmm, PUSH64rmm,
@@ -614,7 +614,7 @@ def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;
def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
let Latency = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
CMPSB, CMPSL, CMPSQ, CMPSW,
@@ -630,7 +630,7 @@ def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
let Latency = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
JCXZ, JECXZ, JRCXZ,
@@ -640,14 +640,14 @@ def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
let Latency = 5;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
}
def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
let Latency = 6;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
}
def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
SHLD16rrCL, SHRD16rrCL,
@@ -659,13 +659,13 @@ def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",
def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
let Latency = 7;
- let ReleaseAtCycles = [7];
+ let ResourceCycles = [7];
}
def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
let Latency = 8;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def : InstRW<[AtomWrite01_8], (instrs LOOPE,
PUSHA16, PUSHA32,
@@ -674,7 +674,7 @@ def : InstRW<[AtomWrite01_8], (instrs LOOPE,
def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
let Latency = 9;
- let ReleaseAtCycles = [9];
+ let ResourceCycles = [9];
}
def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
PUSHF16, PUSHF32, PUSHF64,
@@ -686,256 +686,256 @@ def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F")>;
def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
let Latency = 10;
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
}
def : SchedAlias<WriteFLDC, AtomWrite01_10>;
def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
let Latency = 11;
- let ReleaseAtCycles = [11];
+ let ResourceCycles = [11];
}
def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;
def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
let Latency = 13;
- let ReleaseAtCycles = [13];
+ let ResourceCycles = [13];
}
def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
let Latency = 14;
- let ReleaseAtCycles = [14];
+ let ResourceCycles = [14];
}
def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
let Latency = 17;
- let ReleaseAtCycles = [17];
+ let ResourceCycles = [17];
}
def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
let Latency = 18;
- let ReleaseAtCycles = [18];
+ let ResourceCycles = [18];
}
def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
let Latency = 20;
- let ReleaseAtCycles = [20];
+ let ResourceCycles = [20];
}
def : InstRW<[AtomWrite01_20], (instrs DAS)>;
def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
let Latency = 21;
- let ReleaseAtCycles = [21];
+ let ResourceCycles = [21];
}
def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
let Latency = 22;
- let ReleaseAtCycles = [22];
+ let ResourceCycles = [22];
}
def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
let Latency = 23;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
}
def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
let Latency = 25;
- let ReleaseAtCycles = [25];
+ let ResourceCycles = [25];
}
def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
let Latency = 26;
- let ReleaseAtCycles = [26];
+ let ResourceCycles = [26];
}
def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
let Latency = 29;
- let ReleaseAtCycles = [29];
+ let ResourceCycles = [29];
}
def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
let Latency = 30;
- let ReleaseAtCycles = [30];
+ let ResourceCycles = [30];
}
def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
let Latency = 32;
- let ReleaseAtCycles = [32];
+ let ResourceCycles = [32];
}
def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
let Latency = 45;
- let ReleaseAtCycles = [45];
+ let ResourceCycles = [45];
}
def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;
def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
let Latency = 46;
- let ReleaseAtCycles = [46];
+ let ResourceCycles = [46];
}
def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
let Latency = 48;
- let ReleaseAtCycles = [48];
+ let ResourceCycles = [48];
}
def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
let Latency = 55;
- let ReleaseAtCycles = [55];
+ let ResourceCycles = [55];
}
def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
let Latency = 59;
- let ReleaseAtCycles = [59];
+ let ResourceCycles = [59];
}
def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
let Latency = 63;
- let ReleaseAtCycles = [63];
+ let ResourceCycles = [63];
}
def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
let Latency = 68;
- let ReleaseAtCycles = [68];
+ let ResourceCycles = [68];
}
def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
let Latency = 71;
- let ReleaseAtCycles = [71];
+ let ResourceCycles = [71];
}
def : InstRW<[AtomWrite01_71], (instrs FPREM1,
INVLPG, INVLPGA32, INVLPGA64)>;
def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
let Latency = 72;
- let ReleaseAtCycles = [72];
+ let ResourceCycles = [72];
}
def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
let Latency = 74;
- let ReleaseAtCycles = [74];
+ let ResourceCycles = [74];
}
def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
let Latency = 77;
- let ReleaseAtCycles = [77];
+ let ResourceCycles = [77];
}
def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
let Latency = 78;
- let ReleaseAtCycles = [78];
+ let ResourceCycles = [78];
}
def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
let Latency = 79;
- let ReleaseAtCycles = [79];
+ let ResourceCycles = [79];
}
def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",
"LRETI?(16|32|64)")>;
def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
let Latency = 92;
- let ReleaseAtCycles = [92];
+ let ResourceCycles = [92];
}
def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
let Latency = 94;
- let ReleaseAtCycles = [94];
+ let ResourceCycles = [94];
}
def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
let Latency = 99;
- let ReleaseAtCycles = [99];
+ let ResourceCycles = [99];
}
def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
let Latency = 121;
- let ReleaseAtCycles = [121];
+ let ResourceCycles = [121];
}
def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
let Latency = 127;
- let ReleaseAtCycles = [127];
+ let ResourceCycles = [127];
}
def : InstRW<[AtomWrite01_127], (instrs INT)>;
def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
let Latency = 130;
- let ReleaseAtCycles = [130];
+ let ResourceCycles = [130];
}
def : InstRW<[AtomWrite01_130], (instrs INT3)>;
def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
let Latency = 140;
- let ReleaseAtCycles = [140];
+ let ResourceCycles = [140];
}
def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
let Latency = 141;
- let ReleaseAtCycles = [141];
+ let ResourceCycles = [141];
}
def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
let Latency = 146;
- let ReleaseAtCycles = [146];
+ let ResourceCycles = [146];
}
def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
let Latency = 147;
- let ReleaseAtCycles = [147];
+ let ResourceCycles = [147];
}
def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
let Latency = 168;
- let ReleaseAtCycles = [168];
+ let ResourceCycles = [168];
}
def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
let Latency = 174;
- let ReleaseAtCycles = [174];
+ let ResourceCycles = [174];
}
def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
let Latency = 183;
- let ReleaseAtCycles = [183];
+ let ResourceCycles = [183];
}
def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
let Latency = 202;
- let ReleaseAtCycles = [202];
+ let ResourceCycles = [202];
}
def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index aeeabba45b65ec..c8dafcdeebd75d 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -192,7 +192,7 @@ multiclass PdWriteRes<SchedWrite SchedRW,
list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@@ -265,16 +265,16 @@ def : WriteRes<WriteRMW, [PdStore]>;
// Loads, stores, and moves, not folded with other operations.
////////////////////////////////////////////////////////////////////////////////
-def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ReleaseAtCycles = [2]; }
+def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
def : WriteRes<WriteStore, [PdStore]>;
def : WriteRes<WriteStoreNT, [PdStore]>;
-def : WriteRes<WriteMove, [PdEX01]> { let ReleaseAtCycles = [2]; }
+def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;
// Load/store MXCSR.
// FIXME: These are copy and pasted from WriteLoad/Store.
def : WriteRes<WriteLDMXCSR, [PdLoad]> { let Latency = 5; }
-def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ReleaseAtCycles = [18]; }
+def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
@@ -308,7 +308,7 @@ def : InstRW<[PdWriteXLAT], (instrs XLAT)>;
def PdWriteLARrr : SchedWriteRes<[PdEX01]> {
let Latency = 184;
- let ReleaseAtCycles = [375];
+ let ResourceCycles = [375];
let NumMicroOps = 45;
}
def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
@@ -316,7 +316,7 @@ def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
// Nops don't have dependencies, so there's no actual latency, but we set this
// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
-def : WriteRes<WriteNop, [PdEX01]> { let ReleaseAtCycles = [2]; }
+def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
////////////////////////////////////////////////////////////////////////////////
// Arithmetic.
@@ -326,21 +326,21 @@ defm : PdWriteResExPair<WriteALU, [PdEX01], 1, [2]>;
def PdWriteALURMW : SchedWriteRes<[PdLoad, PdEX01, PdStore]> {
let Latency = 6;
- let ReleaseAtCycles = [3, 2, 1];
+ let ResourceCycles = [3, 2, 1];
let NumMicroOps = 1;
}
def : SchedAlias<WriteALURMW, PdWriteALURMW>;
def PdWriteLXADD : SchedWriteRes<[PdEX01]> {
let Latency = 6;
- let ReleaseAtCycles = [88];
+ let ResourceCycles = [88];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteLXADD], (instrs LXADD8, LXADD16, LXADD32, LXADD64)>;
def PdWriteBMI1 : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBMI1],
@@ -352,7 +352,7 @@ def : InstRW<[PdWriteBMI1],
def PdWriteBMI1m : SchedWriteRes<[PdLoad, PdEX01]> {
let Latency = 6;
- let ReleaseAtCycles = [3, 3];
+ let ResourceCycles = [3, 3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBMI1m],
@@ -365,7 +365,7 @@ def : InstRW<[PdWriteBMI1m],
defm : PdWriteResExPair<WriteADC, [PdEX01], 1, [2]>;
def PdWriteADCSBB64ri32 : SchedWriteRes<[PdEX01]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
}
def : InstRW<[PdWriteADCSBB64ri32], (instrs ADC64ri32, SBB64ri32)>;
@@ -377,21 +377,21 @@ defm : PdWriteRes<WriteXCHG, [PdEX1], 1, [],
def PdWriteCMPXCHG8rr : SchedWriteRes<[PdEX1]> {
let Latency = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 3;
}
def : InstRW<[PdWriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
def PdWriteCMPXCHG8rm : SchedWriteRes<[PdEX1]> {
let Latency = 3;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
let NumMicroOps = 5;
}
def : InstRW<[PdWriteCMPXCHG8rm], (instrs CMPXCHG8rm)>;
def PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm : SchedWriteRes<[PdEX1]> {
let Latency = 3;
- let ReleaseAtCycles = [21];
+ let ResourceCycles = [21];
let NumMicroOps = 6;
}
def : InstRW<[PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm],
@@ -399,21 +399,21 @@ def : InstRW<[PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm],
def PdWriteCMPXCHG8B : SchedWriteRes<[PdEX1]> {
let Latency = 3;
- let ReleaseAtCycles = [26];
+ let ResourceCycles = [26];
let NumMicroOps = 18;
}
def : InstRW<[PdWriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def PdWriteCMPXCHG16B : SchedWriteRes<[PdEX1]> {
let Latency = 3;
- let ReleaseAtCycles = [69];
+ let ResourceCycles = [69];
let NumMicroOps = 22;
}
def : InstRW<[PdWriteCMPXCHG16B], (instrs CMPXCHG16B)>;
def PdWriteXADDm : SchedWriteRes<[PdEX1]> {
let Latency = 6;
- let ReleaseAtCycles = [20];
+ let ResourceCycles = [20];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteXADDm], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
@@ -449,21 +449,21 @@ defm : PdWriteResExPair<WriteCRC32, [PdEX01], 2, [4],
def PdWriteCRC32r32r16 : SchedWriteRes<[PdEX01]> {
let Latency = 5;
- let ReleaseAtCycles = [10];
+ let ResourceCycles = [10];
let NumMicroOps = 5;
}
def : InstRW<[PdWriteCRC32r32r16], (instrs CRC32r32r16)>;
def PdWriteCRC32r32r32 : SchedWriteRes<[PdEX01]> {
let Latency = 6;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 7;
}
def : InstRW<[PdWriteCRC32r32r32], (instrs CRC32r32r32)>;
def PdWriteCRC32r64r64 : SchedWriteRes<[PdEX01]> {
let Latency = 10;
- let ReleaseAtCycles = [17];
+ let ResourceCycles = [17];
let NumMicroOps = 11;
}
def : InstRW<[PdWriteCRC32r64r64], (instrs CRC32r64r64)>;
@@ -472,7 +472,7 @@ defm : PdWriteResExPair<WriteCMOV, [PdEX01]>; // Conditional move.
def PdWriteCMOVm : SchedWriteRes<[PdLoad, PdEX01]> {
let Latency = 5;
- let ReleaseAtCycles = [3, 3];
+ let ResourceCycles = [3, 3];
let NumMicroOps = 2;
}
@@ -494,7 +494,7 @@ def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
def : WriteRes<WriteSETCCStore, [PdEX01, PdStore]>;
def PdWriteSETGEmSETGmSETLEmSETLm : SchedWriteRes<[PdEX01]> {
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
@@ -511,14 +511,14 @@ defm : PdWriteRes<WriteLAHFSAHF, [PdEX01], 2, [4], 2>;
def PdWriteLAHF : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteLAHF], (instrs LAHF)>;
def PdWriteSAHF : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteSAHF], (instrs SAHF)>;
@@ -532,24 +532,24 @@ defm : PdWriteRes<WriteBitTestSetRegLd, [PdEX01, PdLoad], 6, [1, 1], 10>;
def PdWriteBTSIm : SchedWriteRes<[PdEX01, PdLoad]> {
let Latency = 7;
- let ReleaseAtCycles = [42, 1];
+ let ResourceCycles = [42, 1];
let NumMicroOps = 4;
}
def : SchedAlias<WriteBitTestSetImmRMW, PdWriteBTSIm>;
def PdWriteBTSRm : SchedWriteRes<[PdEX01, PdLoad]> {
let Latency = 7;
- let ReleaseAtCycles = [44, 1];
+ let ResourceCycles = [44, 1];
let NumMicroOps = 10;
}
def : SchedAlias<WriteBitTestSetRegRMW, PdWriteBTSRm>;
// This is for simple LEAs with one or two input operands.
-def : WriteRes<WriteLEA, [PdEX01]> { let ReleaseAtCycles = [2]; }
+def : WriteRes<WriteLEA, [PdEX01]> { let ResourceCycles = [2]; }
// This write is used for slow LEA instructions.
def PdWrite3OpsLEA : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// On Piledriver, a slow LEA is either a 3Ops LEA (base, index, offset),
@@ -574,7 +574,7 @@ def PdWriteLEA : SchedWriteVariant<[
def : InstRW<[PdWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def PdWriteLEA16r : SchedWriteRes<[PdEX01]> {
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteLEA16r], (instrs LEA16r)>;
@@ -593,14 +593,14 @@ defm : PdWriteResExPair<WriteBZHI, [PdEX01]>;
def PdWriteBEXTRI : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBEXTRI], (instrs BEXTRI32ri, BEXTRI64ri)>;
def PdWriteBEXTRIm : SchedWriteRes<[PdEX01]> {
let Latency = 2;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBEXTRIm], (instrs BEXTRI32mi, BEXTRI64mi)>;
@@ -616,56 +616,56 @@ defm : PdWriteResExPair<WriteRotateCL, [PdEX01]>;
def PdWriteRCL8rCL : SchedWriteRes<[PdEX01]> {
let Latency = 12;
- let ReleaseAtCycles = [24];
+ let ResourceCycles = [24];
let NumMicroOps = 26;
}
def : InstRW<[PdWriteRCL8rCL], (instrs RCL8rCL)>;
def PdWriteRCR8ri : SchedWriteRes<[PdEX01]> {
let Latency = 12;
- let ReleaseAtCycles = [23];
+ let ResourceCycles = [23];
let NumMicroOps = 23;
}
def : InstRW<[PdWriteRCR8ri], (instrs RCR8ri)>;
def PdWriteRCR8rCL : SchedWriteRes<[PdEX01]> {
let Latency = 11;
- let ReleaseAtCycles = [22];
+ let ResourceCycles = [22];
let NumMicroOps = 24;
}
def : InstRW<[PdWriteRCR8rCL], (instrs RCR8rCL)>;
def PdWriteRCL16rCL : SchedWriteRes<[PdEX01]> {
let Latency = 10;
- let ReleaseAtCycles = [20];
+ let ResourceCycles = [20];
let NumMicroOps = 22;
}
def : InstRW<[PdWriteRCL16rCL], (instrs RCL16rCL)>;
def PdWriteRCR16ri : SchedWriteRes<[PdEX01]> {
let Latency = 10;
- let ReleaseAtCycles = [19];
+ let ResourceCycles = [19];
let NumMicroOps = 19;
}
def : InstRW<[PdWriteRCR16ri], (instrs RCR16ri)>;
def PdWriteRCL3264rCL : SchedWriteRes<[PdEX01]> {
let Latency = 7;
- let ReleaseAtCycles = [14];
+ let ResourceCycles = [14];
let NumMicroOps = 17;
}
def : InstRW<[PdWriteRCL3264rCL], (instrs RCL32rCL, RCL64rCL)>;
def PdWriteRCR3264rCL : SchedWriteRes<[PdEX01]> {
let Latency = 7;
- let ReleaseAtCycles = [13];
+ let ResourceCycles = [13];
let NumMicroOps = 16;
}
def : InstRW<[PdWriteRCR3264rCL], (instrs RCR32rCL, RCR64rCL)>;
def PdWriteRCR32riRCR64ri : SchedWriteRes<[PdEX01]> {
let Latency = 7;
- let ReleaseAtCycles = [14];
+ let ResourceCycles = [14];
let NumMicroOps = 15;
}
def : InstRW<[PdWriteRCR32riRCR64ri], (instrs RCR32ri, RCR64ri)>;
@@ -673,28 +673,28 @@ def : InstRW<[PdWriteRCR32riRCR64ri], (instrs RCR32ri, RCR64ri)>;
def PdWriteRCR16rCL : SchedWriteRes<[PdEX01]> {
let Latency = 9;
- let ReleaseAtCycles = [18];
+ let ResourceCycles = [18];
let NumMicroOps = 20;
}
def : InstRW<[PdWriteRCR16rCL], (instrs RCR16rCL)>;
def PdWriteRCL16ri : SchedWriteRes<[PdEX01]> {
let Latency = 11;
- let ReleaseAtCycles = [21];
+ let ResourceCycles = [21];
let NumMicroOps = 21;
}
def : InstRW<[PdWriteRCL16ri], (instrs RCL16ri)>;
def PdWriteRCL3264ri : SchedWriteRes<[PdEX01]> {
let Latency = 8;
- let ReleaseAtCycles = [15];
+ let ResourceCycles = [15];
let NumMicroOps = 16;
}
def : InstRW<[PdWriteRCL3264ri], (instrs RCL32ri, RCL64ri)>;
def PdWriteRCL8ri : SchedWriteRes<[PdEX01]> {
let Latency = 13;
- let ReleaseAtCycles = [25];
+ let ResourceCycles = [25];
let NumMicroOps = 25;
}
def : InstRW<[PdWriteRCL8ri], (instrs RCL8ri)>;
@@ -705,7 +705,7 @@ defm : PdWriteRes<WriteSHDrrcl, [PdEX01], 3, [8], 7>;
def PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL : SchedWriteRes<[PdEX01]> {
let Latency = 3;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL], (instrs SHLD16rrCL,
@@ -736,7 +736,7 @@ defm : PdWriteRes<WriteFStoreY, [PdStore, PdFPU23, PdFPSTO], 1, [1, 3
def PdWriteMOVHPm : SchedWriteRes<[PdStore, PdFPU23, PdFPSTO]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 3, 1];
+ let ResourceCycles = [1, 3, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteMOVHPm], (instrs MOVHPDmr, MOVHPSmr, VMOVHPDmr, VMOVHPSmr)>;
@@ -769,7 +769,7 @@ defm : X86WriteResPairUnsupported<WriteFAddZ>;
def PdWriteX87Add: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
let Latency = 5;
- let ReleaseAtCycles = [3, 1, 10];
+ let ResourceCycles = [3, 1, 10];
}
def : InstRW<[PdWriteX87Add], (instrs ADD_FI16m, ADD_FI32m, ADD_F32m, ADD_F64m,
SUB_FI16m, SUB_FI32m, SUB_F32m, SUB_F64m,
@@ -808,7 +808,7 @@ defm : X86WriteResPairUnsupported<WriteFMulZ>;
def PdWriteX87Mul: SchedWriteRes<[PdLoad, PdFPU1, PdFPFMA]> {
let Latency = 5;
- let ReleaseAtCycles = [3, 1, 10];
+ let ResourceCycles = [3, 1, 10];
}
def : InstRW<[PdWriteX87Mul], (instrs MUL_FI16m, MUL_FI32m, MUL_F32m, MUL_F64m)>;
@@ -829,7 +829,7 @@ defm : PdWriteResYMMPair<WriteDPPSY, [PdFPU1, PdFPFMA], 27, [2, 25], /*or
def PdWriteVDPPSrri : SchedWriteRes<[PdFPU1, PdFPFMA]> {
let Latency = 27;
- let ReleaseAtCycles = [1, 14];
+ let ResourceCycles = [1, 14];
let NumMicroOps = 17;
}
def : InstRW<[PdWriteVDPPSrri], (instrs VDPPSrri)>;
@@ -851,7 +851,7 @@ defm : X86WriteResPairUnsupported<WriteFDivZ>;
def PdWriteX87Div: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
let Latency = 9;
- let ReleaseAtCycles = [3, 1, 18];
+ let ResourceCycles = [3, 1, 18];
}
def : InstRW<[PdWriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
DIVR_FI16m, DIVR_FI32m,
@@ -882,21 +882,21 @@ defm : X86WriteResPairUnsupported<WriteFRndZ>;
def PdWriteVFRCZP : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVFRCZP], (instrs VFRCZPDrr, VFRCZPSrr)>;
def PdWriteVFRCZS : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
- let ReleaseAtCycles = [10, 1];
+ let ResourceCycles = [10, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVFRCZS], (instrs VFRCZSDrr, VFRCZSSrr)>;
def PdWriteVFRCZm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 15;
- let ReleaseAtCycles = [2, 1];
+ let ResourceCycles = [2, 1];
let NumMicroOps = 3;
}
def : InstRW<[PdWriteVFRCZm], (instrs VFRCZPDrm, VFRCZPSrm,
@@ -904,14 +904,14 @@ def : InstRW<[PdWriteVFRCZm], (instrs VFRCZPDrm, VFRCZPSrm,
def PdWriteVFRCZY : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteVFRCZY], (instrs VFRCZPSYrr, VFRCZPDYrr)>;
def PdWriteVFRCZYm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 15;
- let ReleaseAtCycles = [4, 1];
+ let ResourceCycles = [4, 1];
let NumMicroOps = 8;
}
def : InstRW<[PdWriteVFRCZYm], (instrs VFRCZPSYrm, VFRCZPDYrm)>;
@@ -930,7 +930,7 @@ defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 7;
- let ReleaseAtCycles = [1, 3];
+ let ResourceCycles = [1, 3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
@@ -952,27 +952,27 @@ defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
def PdWriteVEXTRACTF128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[PdWriteVEXTRACTF128rr], (instrs VEXTRACTF128rr)>;
def PdWriteVEXTRACTF128mr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 7;
- let ReleaseAtCycles = [1, 4];
+ let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVEXTRACTF128mr], (instrs VEXTRACTF128mr)>;
def PdWriteVPERM2F128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 4;
- let ReleaseAtCycles = [1, 6];
+ let ResourceCycles = [1, 6];
let NumMicroOps = 8;
}
def : InstRW<[PdWriteVPERM2F128rr], (instrs VPERM2F128rr)>;
def PdWriteVPERM2F128rm : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 8; // 4 + 4
- let ReleaseAtCycles = [1, 8];
+ let ResourceCycles = [1, 8];
let NumMicroOps = 10;
}
def : InstRW<[PdWriteVPERM2F128rm], (instrs VPERM2F128rm)>;
@@ -1012,7 +1012,7 @@ defm : PdWriteResXMMPair<WriteCvtI2SD, [PdFPU0, PdFPCVT, PdFPSTO], 4, [], 2>;
def PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr : SchedWriteRes<[PdFPU0, PdFPCVT, PdFPSTO]> {
let Latency = 13;
- let ReleaseAtCycles = [1, 3, 1];
+ let ResourceCycles = [1, 3, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr], (instrs CVTSI642SDrr, CVTSI642SSrr, CVTSI2SDrr, CVTSI2SSrr)>;
@@ -1161,13 +1161,13 @@ defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
def PdWriteVPPERM : SchedWriteRes<[PdFPU1, PdFPXBR]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
}
def : InstRW<[PdWriteVPPERM], (instrs VPPERMrrr, VPPERMrrr_REV)>;
def PdWriteVPPERMLd : SchedWriteRes<[PdFPU1, PdFPXBR, PdLoad]> {
let Latency = 7;
- let ReleaseAtCycles = [1, 1, 3];
+ let ResourceCycles = [1, 1, 3];
}
def : InstRW<[PdWriteVPPERMLd], (instrs VPPERMrrm, VPPERMrmr)>;
@@ -1208,7 +1208,7 @@ defm : PdWriteRes<WriteVecExtractSt, [PdFPU1, PdFPSTO, PdStore], 13, [2, 1, 1],
def PdWriteEXTRQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 3];
+ let ResourceCycles = [1, 3];
}
def : InstRW<[PdWriteEXTRQ], (instrs EXTRQ, EXTRQI)>;
@@ -1277,7 +1277,7 @@ defm : PdWriteResXMMPair<WriteCLMul, [PdFPU0, PdFPMMA], 12, [1, 7], 5, 1>;
def PdWriteVPCLMULQDQrr : SchedWriteRes<[PdFPU0, PdFPMMA]> {
let Latency = 12;
- let ReleaseAtCycles = [1, 7];
+ let ResourceCycles = [1, 7];
let NumMicroOps = 6;
}
def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
@@ -1288,13 +1288,13 @@ def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
def PdWriteINSERTQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[PdWriteINSERTQ], (instrs INSERTQ)>;
def PdWriteINSERTQI : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 3];
+ let ResourceCycles = [1, 3];
}
def : InstRW<[PdWriteINSERTQI], (instrs INSERTQI)>;
@@ -1304,7 +1304,7 @@ def : InstRW<[PdWriteINSERTQI], (instrs INSERTQI)>;
def PdWriteVBROADCASTYLd : SchedWriteRes<[PdLoad, PdFPU01, PdFPFMA]> {
let Latency = 6;
- let ReleaseAtCycles = [1, 2, 4];
+ let ResourceCycles = [1, 2, 4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm,
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 8b7d501981b1e6..222d65ca597177 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -125,7 +125,7 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -133,7 +133,7 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 3);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -145,7 +145,7 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -153,7 +153,7 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -165,7 +165,7 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -173,7 +173,7 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
- let ReleaseAtCycles = !listconcat([2], Res);
+ let ResourceCycles = !listconcat([2], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -313,49 +313,49 @@ def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
def JWriteCMPXCHG8rr : SchedWriteRes<[JALU01]> {
let Latency = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 3;
}
def JWriteLOCK_CMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 16;
- let ReleaseAtCycles = [3,16,16];
+ let ResourceCycles = [3,16,16];
let NumMicroOps = 5;
}
def JWriteLOCK_CMPXCHGrm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 17;
- let ReleaseAtCycles = [3,17,17];
+ let ResourceCycles = [3,17,17];
let NumMicroOps = 6;
}
def JWriteCMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
- let ReleaseAtCycles = [3,1,1];
+ let ResourceCycles = [3,1,1];
let NumMicroOps = 5;
}
def JWriteCMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
- let ReleaseAtCycles = [3,1,1];
+ let ResourceCycles = [3,1,1];
let NumMicroOps = 18;
}
def JWriteCMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 32;
- let ReleaseAtCycles = [6,1,1];
+ let ResourceCycles = [6,1,1];
let NumMicroOps = 28;
}
def JWriteLOCK_CMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
- let ReleaseAtCycles = [3,19,19];
+ let ResourceCycles = [3,19,19];
let NumMicroOps = 18;
}
def JWriteLOCK_CMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 38;
- let ReleaseAtCycles = [6,38,38];
+ let ResourceCycles = [6,38,38];
let NumMicroOps = 28;
}
@@ -394,7 +394,7 @@ def : InstRW<[JWriteCMPXCHGVariant,
def JWriteLOCK_ALURMW : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
- let ReleaseAtCycles = [1,19,19];
+ let ResourceCycles = [1,19,19];
let NumMicroOps = 1;
}
@@ -409,7 +409,7 @@ def : InstRW<[JWriteLOCK_ALURMWVariant], (instrs INC8m, INC16m, INC32m, INC64m,
def JWriteXCHG8rr_XADDrr : SchedWriteRes<[JALU01]> {
let Latency = 2;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 3;
}
def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
@@ -434,7 +434,7 @@ def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
// latency is assumed to be 3cy.
def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 3; // load-to-use latency
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 3;
}
@@ -451,7 +451,7 @@ def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// execution. This write is used to specifically set that operand latency.
def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 3;
}
@@ -463,19 +463,19 @@ def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// set the instruction latency to 16cy.
def JWriteXCHGrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def JWriteXADDrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 11;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def JWriteXCHGrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 16;
- let ReleaseAtCycles = [16, 16];
+ let ResourceCycles = [16, 16];
let NumMicroOps = 1;
}
@@ -798,7 +798,7 @@ defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>;
def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 4];
+ let ResourceCycles = [1, 4];
}
def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
@@ -811,7 +811,7 @@ def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;
def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
let Latency = 6;
- let ReleaseAtCycles = [1, 2, 4];
+ let ResourceCycles = [1, 2, 4];
let NumMicroOps = 2;
}
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
@@ -836,7 +836,7 @@ def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;
def JWriteMASKMOVDQU: SchedWriteRes<[JFPU0, JFPA, JFPU1, JSTC, JLAGU, JSAGU, JALU01]> {
let Latency = 34;
- let ReleaseAtCycles = [1, 1, 2, 2, 2, 16, 42];
+ let ResourceCycles = [1, 1, 2, 2, 2, 16, 42];
let NumMicroOps = 63;
}
def : InstRW<[JWriteMASKMOVDQU], (instrs MASKMOVDQU, MASKMOVDQU64,
@@ -960,7 +960,7 @@ def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def JSlowLEA16r : SchedWriteRes<[JALU01]> {
let Latency = 3;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
}
def : InstRW<[JSlowLEA16r], (instrs LEA16r)>;
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index d5fa9f7f962822..ff50c6dfc621ad 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -66,7 +66,7 @@ multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -74,7 +74,7 @@ multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 3).
def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !listconcat([1], Res);
+ let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -139,7 +139,7 @@ defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional mo
def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
- let ReleaseAtCycles = [2,1];
+ let ResourceCycles = [2,1];
}
defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;
@@ -413,7 +413,7 @@ def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {
def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 4;
let NumMicroOps = 5;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
////////////////////////////////////////////////////////////////////////////////
@@ -465,7 +465,7 @@ def : WriteRes<WriteNop, []>;
def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
let Latency = 4;
let NumMicroOps = 2;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
}
def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
MMX_PSUBQrr, PSUBQrr,
@@ -474,14 +474,14 @@ def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
def SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> {
let Latency = 5;
let NumMicroOps = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>;
def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
let Latency = 7;
let NumMicroOps = 3;
- let ReleaseAtCycles = [1,8];
+ let ResourceCycles = [1,8];
}
def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
@@ -491,7 +491,7 @@ def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
def SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index e39bcf807a0c00..0e001638d03d95 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -136,7 +136,7 @@ multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -144,7 +144,7 @@ multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -157,7 +157,7 @@ multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -165,7 +165,7 @@ multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -455,12 +455,12 @@ defm : ZnWriteResFpuPair<WriteVecInsert, [ZnFPU], 1>;
def : WriteRes<WriteVecExtract, [ZnFPU12, ZnFPU2]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [ZnAGU, ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2, 3];
+ let ResourceCycles = [1, 2, 3];
}
// MOVMSK Instructions.
@@ -471,7 +471,7 @@ def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
def : WriteRes<WriteVecMOVMSKY, [ZnFPU2]> {
let NumMicroOps = 2;
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// AES Instructions.
@@ -869,7 +869,7 @@ def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
// FICOM(P).
@@ -910,12 +910,12 @@ def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>;
def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 8;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 9;
- let ReleaseAtCycles = [1, 3];
+ let ResourceCycles = [1, 3];
}
def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
@@ -938,7 +938,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
@@ -947,7 +947,7 @@ def : InstRW<[ZnWriteVPBROADCAST128Ld],
def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
@@ -977,7 +977,7 @@ def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
@@ -1004,14 +1004,14 @@ def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [5, 1, 2];
+ let ResourceCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
@@ -1027,12 +1027,12 @@ def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr,
def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> {
let Latency = 9;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
// VINSERTF128 / VINSERTI128.
// y,y,x,i.
@@ -1051,7 +1051,7 @@ def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> {
def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// CVTPD2PS.
@@ -1072,7 +1072,7 @@ def : SchedAlias<WriteCvtPD2PSLd, ZnWriteCVTPD2PSLd>;
def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def : SchedAlias<WriteCvtPD2PSYLd, ZnWriteCVTPD2PSYLd>;
// z,m512
@@ -1121,7 +1121,7 @@ def : SchedAlias<WriteCvtSS2SD, ZnWriteCVTSS2SDr>;
def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, ZnWriteCVTSS2SDLd>;
@@ -1243,13 +1243,13 @@ def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
// x,x.
def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
// x,m.
def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 9;
- let ReleaseAtCycles = [1,2];
+ let ResourceCycles = [1,2];
}
def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index ecaca70bb67755..117885406a0a34 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -135,7 +135,7 @@ multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -143,7 +143,7 @@ multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -156,7 +156,7 @@ multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@@ -164,7 +164,7 @@ multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
- let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
+ let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@@ -454,12 +454,12 @@ defm : Zn2WriteResFpuPair<WriteVecInsert, [Zn2FPU], 1>;
def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2, 3];
+ let ResourceCycles = [1, 2, 3];
}
// MOVMSK Instructions.
@@ -470,7 +470,7 @@ def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
let NumMicroOps = 2;
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
}
// AES Instructions.
@@ -879,7 +879,7 @@ def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1,3];
+ let ResourceCycles = [1,3];
}
// FICOM(P).
@@ -920,12 +920,12 @@ def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 8;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 9;
- let ReleaseAtCycles = [1, 3];
+ let ResourceCycles = [1, 3];
}
def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
@@ -948,7 +948,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
@@ -957,7 +957,7 @@ def : InstRW<[Zn2WriteVPBROADCAST128Ld],
def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
let Latency = 8;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
@@ -1012,14 +1012,14 @@ def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
- let ReleaseAtCycles = [5, 1, 2];
+ let ResourceCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
@@ -1035,7 +1035,7 @@ def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr,
def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
let Latency = 2;
-// let ReleaseAtCycles = [2];
+// let ResourceCycles = [2];
}
def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
let Latency = 9;
@@ -1124,7 +1124,7 @@ def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
let Latency = 10;
let NumMicroOps = 2;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index d90c8bd284eb0a..fd617765b16767 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -402,7 +402,7 @@ multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@@ -501,7 +501,7 @@ defm : Zn3WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver3Model.LoadLa
def Zn3WriteMOVSlow : SchedWriteRes<[Zn3AGU012, Zn3Load]> {
let Latency = !add(Znver3Model.LoadLatency, 1);
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
@@ -515,14 +515,14 @@ def : InstRW<[WriteMove], (instrs COPY)>;
def Zn3WriteMOVBE16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = Znver3Model.LoadLatency;
- let ReleaseAtCycles = [1, 1, 4];
+ let ResourceCycles = [1, 1, 4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMOVBE16rm], (instrs MOVBE16rm)>;
def Zn3WriteMOVBEmr : SchedWriteRes<[Zn3ALU0123, Zn3AGU012, Zn3Store]> {
let Latency = Znver3Model.StoreLatency;
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
@@ -532,7 +532,7 @@ defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer
def Zn3WriteALUSlow : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
@@ -543,21 +543,21 @@ def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
def Zn3WriteMoveExtend : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
def Zn3WriteMaterialize32bitImm: SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
def Zn3WritePDEP_PEXT : SchedWriteRes<[Zn3ALU1]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
@@ -567,7 +567,7 @@ defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + f
def Zn3WriteADC8mr_SBB8mr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123, Zn3Store]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 1, 7, 1];
+ let ResourceCycles = [1, 1, 7, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
@@ -578,7 +578,7 @@ defm : Zn3WriteResInt<WriteLEA, [Zn3AGU012], 1, [1], 1>; // LEA instructions
// This write is used for slow LEA instructions.
def Zn3Write3OpsLEA : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -605,7 +605,7 @@ def : InstRW<[Zn3WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def Zn3SlowLEA16r : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 2;
}
@@ -634,7 +634,7 @@ defm : Zn3WriteResIntPair<WriteCMPXCHG, [Zn3ALU0123], 3, [12], 5>; // Compare an
def Zn3WriteCMPXCHG8rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 3;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 3;
}
def : InstRW<[Zn3WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
@@ -643,42 +643,42 @@ defm : Zn3WriteResInt<WriteCMPXCHGRMW, [Zn3ALU0123], 3, [12], 6>; // Compare
def Zn3WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
- let ReleaseAtCycles = [1, 1, 12];
+ let ResourceCycles = [1, 1, 12];
let NumMicroOps = !add(Zn3WriteCMPXCHG8rr.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
def Zn3WriteCMPXCHG8B : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 3; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [24];
+ let ResourceCycles = [24];
let NumMicroOps = 19;
}
def : InstRW<[Zn3WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def Zn3WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 4; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [59];
+ let ResourceCycles = [59];
let NumMicroOps = 28;
}
def : InstRW<[Zn3WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
def Zn3WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
def Zn3WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 5;
}
def : InstRW<[Zn3WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
def Zn3WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
@@ -702,7 +702,7 @@ defm : Zn3WriteResIntPair<WritePOPCNT, [Zn3ALU0123], 1, [1], 1>; // Bit populati
def Zn3WritePOPCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WritePOPCNT16rr], (instrs POPCNT16rr)>;
@@ -711,7 +711,7 @@ defm : Zn3WriteResIntPair<WriteLZCNT, [Zn3ALU0123], 1, [1], 1>; // Leading zero
def Zn3WriteLZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteLZCNT16rr], (instrs LZCNT16rr)>;
@@ -720,7 +720,7 @@ defm : Zn3WriteResIntPair<WriteTZCNT, [Zn3ALU12], 2, [1], 2>; // Trailing zero c
def Zn3WriteTZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteTZCNT16rr], (instrs TZCNT16rr)>;
@@ -746,7 +746,7 @@ defm : Zn3WriteResIntPair<WriteRotate, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn3WriteRotateR1 : SchedWriteRes<[Zn3ALU12]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
@@ -754,7 +754,7 @@ def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def Zn3WriteRotateM1 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteRotateR1.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
@@ -762,28 +762,28 @@ def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
def Zn3WriteRotateRightRI : SchedWriteRes<[Zn3ALU12]> {
let Latency = 3;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn3WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def Zn3WriteRotateRightMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRI.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateRightRI.NumMicroOps, 3);
}
def : InstRW<[Zn3WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
def Zn3WriteRotateLeftRI : SchedWriteRes<[Zn3ALU12]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn3WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def Zn3WriteRotateLeftMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRI.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateLeftRI.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
@@ -792,28 +792,28 @@ defm : Zn3WriteResIntPair<WriteRotateCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn3WriteRotateRightRCL : SchedWriteRes<[Zn3ALU12]> {
let Latency = 3;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn3WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
def Zn3WriteRotateRightMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRCL.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateRightRCL.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
def Zn3WriteRotateLeftRCL : SchedWriteRes<[Zn3ALU12]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn3WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
def Zn3WriteRotateLeftMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRCL.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateLeftRCL.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
@@ -850,7 +850,7 @@ defm : Zn3WriteResXMM<WriteFStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency
def Zn3WriteWriteFStoreMMX : SchedWriteRes<[Zn3FPSt, Zn3Store]> {
let Latency = 2; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteWriteFStoreMMX], (instrs MOVHPDmr, MOVHPSmr,
@@ -871,7 +871,7 @@ defm : Zn3WriteResXMMPair<WriteFAdd, [Zn3FPFAdd01], 3, [1], 1>; // Floating poi
def Zn3WriteX87Arith : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 24];
+ let ResourceCycles = [1, 1, 24];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
@@ -881,7 +881,7 @@ def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
def Zn3WriteX87Div : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 62];
+ let ResourceCycles = [1, 1, 62];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
@@ -989,21 +989,21 @@ defm : Zn3WriteResXMM<WriteVecStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLate
def Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn3FPFMisc0]> {
let Latency = 4;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
def Zn3WriteVEXTRACTI128mr : SchedWriteRes<[Zn3FPFMisc0, Zn3FPSt, Zn3Store]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
def Zn3WriteVINSERTF128rmr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPFMisc0]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
@@ -1021,14 +1021,14 @@ defm : Zn3WriteResXMM<WriteVecMoveFromGpr, [Zn3FPLd01], 1, [2], 1>;
def Zn3WriteMOVMMX : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
def Zn3WriteMOVMMXSlow : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 4];
+ let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
@@ -1037,14 +1037,14 @@ defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
def Zn3WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
@@ -1053,7 +1053,7 @@ defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteVecALUXSlow : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
@@ -1069,7 +1069,7 @@ def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
def Zn3WriteVecALUXMMX : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUXMMX], (instrs MMX_PABSBrr, MMX_PABSDrr, MMX_PABSWrr,
@@ -1082,7 +1082,7 @@ defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteVecALUYSlow : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
@@ -1157,7 +1157,7 @@ defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; // Double -> Integer (ZMM).
def Zn3WriteCvtPD2IMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtPD2IMMX], (instrs MMX_CVTPD2PIrm, MMX_CVTTPD2PIrm, MMX_CVTPD2PIrr, MMX_CVTTPD2PIrr)>;
@@ -1175,7 +1175,7 @@ defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; // Integer -> Double (ZMM).
def Zn3WriteCvtI2PDMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 2;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtI2PDMMX], (instrs MMX_CVTPI2PDrm, MMX_CVTPI2PDrr)>;
@@ -1187,7 +1187,7 @@ defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; // Integer -> Float (ZMM).
def Zn3WriteCvtI2PSMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtI2PSMMX], (instrs MMX_CVTPI2PSrr)>;
@@ -1218,70 +1218,70 @@ defm : Zn3WriteResIntPair<WriteCRC32, [Zn3ALU1], 3, [1], 1>;
def Zn3WriteSHA1MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
def Zn3WriteSHA1MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteSHA1MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
def Zn3WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
def Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
}
def : InstRW<[Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
def Zn3WriteSHA256MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
def Zn3Writerm_SHA256MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG1rr.Latency);
- let ReleaseAtCycles = [1, 1, 3];
+ let ResourceCycles = [1, 1, 3];
let NumMicroOps = !add(Zn3WriteSHA256MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn3Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
def Zn3WriteSHA256MSG2rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 3;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def : InstRW<[Zn3WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
def Zn3WriteSHA256MSG2rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG2rr.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteSHA256MSG2rr.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
def Zn3WriteSHA1RNDS4rri : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 6;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
def Zn3WriteSHA256RNDS2rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
@@ -1316,14 +1316,14 @@ defm : Zn3WriteResInt<WriteSystem, [Zn3ALU0123], 100, [100], 100>;
def Zn3WriteVZEROUPPER : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 0; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVZEROUPPER], (instrs VZEROUPPER)>;
def Zn3WriteVZEROALL : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 10; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [24];
+ let ResourceCycles = [24];
let NumMicroOps = 18;
}
def : InstRW<[Zn3WriteVZEROALL], (instrs VZEROALL)>;
@@ -1335,42 +1335,42 @@ defm : Zn3WriteResYMMPair<WriteShuffle256, [Zn3FPVShuf], 2, [1], 1>; // 256-bit
def Zn3WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn3FPVShuf]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
def Zn3WriteVPERM2F128rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERM2I128rr_VPERM2F128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
def Zn3WriteVPERMPSYrm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, 7);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 3;
}
def : InstRW<[Zn3WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
def Zn3WriteVPERMYri : SchedWriteRes<[Zn3FPVShuf]> {
let Latency = 6;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
def Zn3WriteVPERMPDYmi : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteVPERMYri.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
def Zn3WriteVPERMDYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, 5);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteVPERMDYm], (instrs VPERMQYmi, VPERMDYrm)>;
@@ -1389,14 +1389,14 @@ defm : Zn3WriteResInt<WriteFence, [Zn3ALU0123], 1, [100], 1>;
def Zn3WriteLFENCE : SchedWriteRes<[Zn3LSU]> {
let Latency = 1;
- let ReleaseAtCycles = [30];
+ let ResourceCycles = [30];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteLFENCE], (instrs LFENCE)>;
def Zn3WriteSFENCE : SchedWriteRes<[Zn3LSU]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSFENCE], (instrs SFENCE)>;
@@ -1411,7 +1411,7 @@ defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not
def Zn3WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
@@ -1420,7 +1420,7 @@ def : InstRW<[Zn3WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
def Zn3WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver4.td b/llvm/lib/Target/X86/X86ScheduleZnver4.td
index 405000f0851e9d..1c585e80d86c4f 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver4.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver4.td
@@ -402,7 +402,7 @@ multiclass __Zn4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
- let ReleaseAtCycles = Res;
+ let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@@ -515,7 +515,7 @@ defm : Zn4WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver4Model.LoadLa
def Zn4WriteMOVSlow : SchedWriteRes<[Zn4AGU012, Zn4Load]> {
let Latency = !add(Znver4Model.LoadLatency, 1);
- let ReleaseAtCycles = [3, 1];
+ let ResourceCycles = [3, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
@@ -529,14 +529,14 @@ def : InstRW<[WriteMove], (instrs COPY)>;
def Zn4WriteMOVBE16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = Znver4Model.LoadLatency;
- let ReleaseAtCycles = [1, 1, 4];
+ let ResourceCycles = [1, 1, 4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMOVBE16rm], (instrs MOVBE16rm)>;
def Zn4WriteMOVBEmr : SchedWriteRes<[Zn4ALU0123, Zn4AGU012, Zn4Store]> {
let Latency = Znver4Model.StoreLatency;
- let ReleaseAtCycles = [4, 1, 1];
+ let ResourceCycles = [4, 1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
@@ -546,7 +546,7 @@ defm : Zn4WriteResIntPair<WriteALU, [Zn4ALU0123], 1, [1], 1>; // Simple integer
def Zn4WriteALUSlow : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
@@ -557,21 +557,21 @@ def : InstRW<[Zn4WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
def Zn4WriteMoveExtend : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
def Zn4WriteMaterialize32bitImm: SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
def Zn4WritePDEP_PEXT : SchedWriteRes<[Zn4ALU1]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
@@ -581,7 +581,7 @@ defm : Zn4WriteResIntPair<WriteADC, [Zn4ALU0123], 1, [4], 1>; // Integer ALU + f
def Zn4WriteADC8mr_SBB8mr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123, Zn4Store]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 1, 7, 1];
+ let ResourceCycles = [1, 1, 7, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
@@ -592,7 +592,7 @@ defm : Zn4WriteResInt<WriteLEA, [Zn4AGU012], 1, [1], 1>; // LEA instructions
// This write is used for slow LEA instructions.
def Zn4Write3OpsLEA : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -619,7 +619,7 @@ def : InstRW<[Zn4WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def Zn4SlowLEA16r : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 2;
}
@@ -648,7 +648,7 @@ defm : Zn4WriteResIntPair<WriteCMPXCHG, [Zn4ALU0123], 3, [12], 5>; // Compare an
def Zn4WriteCMPXCHG8rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 3;
- let ReleaseAtCycles = [12];
+ let ResourceCycles = [12];
let NumMicroOps = 3;
}
def : InstRW<[Zn4WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
@@ -657,42 +657,42 @@ defm : Zn4WriteResInt<WriteCMPXCHGRMW, [Zn4ALU0123], 3, [12], 6>; // Compare
def Zn4WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteCMPXCHG8rr.Latency);
- let ReleaseAtCycles = [1, 1, 12];
+ let ResourceCycles = [1, 1, 12];
let NumMicroOps = !add(Zn4WriteCMPXCHG8rr.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 3; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [24];
+ let ResourceCycles = [24];
let NumMicroOps = 19;
}
def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def Zn4WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 4; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [59];
+ let ResourceCycles = [59];
let NumMicroOps = 28;
}
def : InstRW<[Zn4WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
def Zn4WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
def Zn4WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 5;
}
def : InstRW<[Zn4WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
def Zn4WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
@@ -716,7 +716,7 @@ defm : Zn4WriteResIntPair<WritePOPCNT, [Zn4ALU0123], 1, [1], 1>; // Bit populati
def Zn4WritePOPCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePOPCNT16rr], (instrs POPCNT16rr)>;
@@ -725,7 +725,7 @@ defm : Zn4WriteResIntPair<WriteLZCNT, [Zn4ALU0123], 1, [1], 1>; // Leading zero
def Zn4WriteLZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteLZCNT16rr], (instrs LZCNT16rr)>;
@@ -734,7 +734,7 @@ defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 2, [1], 2>; // Trailing zero c
def Zn4WriteTZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteTZCNT16rr], (instrs TZCNT16rr)>;
@@ -760,7 +760,7 @@ defm : Zn4WriteResIntPair<WriteRotate, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn4WriteRotateR1 : SchedWriteRes<[Zn4ALU12]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
@@ -768,7 +768,7 @@ def : InstRW<[Zn4WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def Zn4WriteRotateM1 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateR1.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteRotateR1.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
@@ -776,28 +776,28 @@ def : InstRW<[Zn4WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
def Zn4WriteRotateRightRI : SchedWriteRes<[Zn4ALU12]> {
let Latency = 3;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn4WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def Zn4WriteRotateRightMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRI.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateRightRI.NumMicroOps, 3);
}
def : InstRW<[Zn4WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
def Zn4WriteRotateLeftRI : SchedWriteRes<[Zn4ALU12]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn4WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def Zn4WriteRotateLeftMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRI.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateLeftRI.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
@@ -806,28 +806,28 @@ defm : Zn4WriteResIntPair<WriteRotateCL, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn4WriteRotateRightRCL : SchedWriteRes<[Zn4ALU12]> {
let Latency = 3;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn4WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
def Zn4WriteRotateRightMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRCL.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateRightRCL.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
def Zn4WriteRotateLeftRCL : SchedWriteRes<[Zn4ALU12]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn4WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
def Zn4WriteRotateLeftMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRCL.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateLeftRCL.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
@@ -864,7 +864,7 @@ defm : Zn4WriteResXMM<WriteFStore, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency
def Zn4WriteWriteFStoreMMX : SchedWriteRes<[Zn4FPSt, Zn4Store]> {
let Latency = 2; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteWriteFStoreMMX], (instrs MOVHPDmr, MOVHPSmr,
@@ -885,7 +885,7 @@ defm : Zn4WriteResXMMPair<WriteFAdd, [Zn4FPFAdd01], 3, [1], 1>; // Floating poi
def Zn4WriteX87Arith : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 24];
+ let ResourceCycles = [1, 1, 24];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
@@ -895,7 +895,7 @@ def : InstRW<[Zn4WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
def Zn4WriteX87Div : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1, 1, 62];
+ let ResourceCycles = [1, 1, 62];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
@@ -1004,21 +1004,21 @@ defm : Zn4WriteResXMM<WriteVecStoreX, [Zn4FPSt, Zn4Store], Znver4Model.StoreLate
def Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn4FPFMisc0]> {
let Latency = 4;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
def Zn4WriteVEXTRACTI128mr : SchedWriteRes<[Zn4FPFMisc0, Zn4FPSt, Zn4Store]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
def Zn4WriteVINSERTF128rmr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPFMisc0]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
@@ -1036,14 +1036,14 @@ defm : Zn4WriteResXMM<WriteVecMoveFromGpr, [Zn4FPLd01], 1, [2], 1>;
def Zn4WriteMOVMMX : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 2];
+ let ResourceCycles = [1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
def Zn4WriteMOVMMXSlow : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
let Latency = 1;
- let ReleaseAtCycles = [1, 4];
+ let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
@@ -1052,14 +1052,14 @@ defm : Zn4WriteResXMMPair<WriteVecALU, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
def Zn4WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
let Latency = 3;
- let ReleaseAtCycles = [1, 1];
+ let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
@@ -1068,7 +1068,7 @@ defm : Zn4WriteResXMMPair<WriteVecALUX, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteVecALUXSlow : SchedWriteRes<[Zn4FPVAdd01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
@@ -1084,7 +1084,7 @@ def : InstRW<[Zn4WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
def Zn4WriteVecOpMask : SchedWriteRes<[Zn4FPOpMask01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMask], (instrs KADDBrr, KADDDrr, KADDQrr, KADDWrr,
@@ -1102,14 +1102,14 @@ def : InstRW<[Zn4WriteVecOpMask], (instrs KADDBrr, KADDDrr, KADDQrr, KADDWrr,
def Zn4WriteVecOpMaskMemMov : SchedWriteRes<[Zn4FPOpMask4]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMaskMemMov], (instrs KMOVBmk, KMOVDmk, KMOVQmk, KMOVWmk)>;
def Zn4WriteVecOpMaskKRMov : SchedWriteRes<[Zn4FPOpMask4]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMaskKRMov], (instrs KMOVBkr, KMOVDkr, KMOVQkr, KMOVWkr)>;
@@ -1117,7 +1117,7 @@ def : InstRW<[Zn4WriteVecOpMaskKRMov], (instrs KMOVBkr, KMOVDkr, KMOVQkr, KMOVWk
def Zn4WriteVecALU2Slow : SchedWriteRes<[Zn4FPVAdd12]> {
// TODO: All align instructions are expected to be of 4 cycle latency
let Latency = 4;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALU2Slow], (instrs VALIGNDZrri, VALIGNDZ128rri, VALIGNDZ256rri,
@@ -1127,7 +1127,7 @@ defm : Zn4WriteResYMMPair<WriteVecALUY, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteVecALUYSlow : SchedWriteRes<[Zn4FPVAdd01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
@@ -1203,7 +1203,7 @@ defm : Zn4WriteResZMMPair<WriteCvtPD2IZ, [Zn4FPFCvt01], 3, [4], 2>; // Double ->
def Zn4WriteCvtPD2IMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
defm : Zn4WriteResXMMPair<WriteCvtSS2I, [Zn4FPFCvt01], 5, [5], 2>; // Float -> Integer.
@@ -1219,7 +1219,7 @@ defm : Zn4WriteResZMMPair<WriteCvtI2PDZ, [Zn4FPFCvt01], 4, [4], 4, /*LoadUOps=*/
def Zn4WriteCvtI2PDMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 2;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 2;
}
@@ -1230,7 +1230,7 @@ defm : Zn4WriteResZMMPair<WriteCvtI2PSZ, [Zn4FPFCvt01], 3, [2], 2>; // Integer -
def Zn4WriteCvtI2PSMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
@@ -1261,70 +1261,70 @@ defm : Zn4WriteResIntPair<WriteCRC32, [Zn4ALU1], 3, [1], 1>;
def Zn4WriteSHA1MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
def Zn4WriteSHA1MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG1rr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteSHA1MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
def Zn4WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 1;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
def Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
}
def : InstRW<[Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
def Zn4WriteSHA256MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 2;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
def Zn4Writerm_SHA256MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG1rr.Latency);
- let ReleaseAtCycles = [1, 1, 3];
+ let ResourceCycles = [1, 1, 3];
let NumMicroOps = !add(Zn4WriteSHA256MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn4Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
def Zn4WriteSHA256MSG2rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 3;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 4;
}
def : InstRW<[Zn4WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
def Zn4WriteSHA256MSG2rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG2rr.Latency);
- let ReleaseAtCycles = [1, 1, 8];
+ let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteSHA256MSG2rr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
def Zn4WriteSHA1RNDS4rri : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 6;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
def Zn4WriteSHA256RNDS2rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 4;
- let ReleaseAtCycles = [8];
+ let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
@@ -1359,14 +1359,14 @@ defm : Zn4WriteResInt<WriteSystem, [Zn4ALU0123], 100, [100], 100>;
def Zn4WriteVZEROUPPER : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 0; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVZEROUPPER], (instrs VZEROUPPER)>;
def Zn4WriteVZEROALL : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 10; // FIXME: not from llvm-exegesis
- let ReleaseAtCycles = [24];
+ let ResourceCycles = [24];
let NumMicroOps = 18;
}
def : InstRW<[Zn4WriteVZEROALL], (instrs VZEROALL)>;
@@ -1378,56 +1378,56 @@ defm : Zn4WriteResYMMPair<WriteShuffle256, [Zn4FPVShuf], 1, [1], 1>; // 256-bit
def Zn4WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 3;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
def Zn4WriteVPERM2F128rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERM2I128rr_VPERM2F128rr.Latency);
- let ReleaseAtCycles = [1, 1, 1];
+ let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
def Zn4WriteVPERMPSYrr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 7;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
def Zn4WriteVPERMPSYrm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMPSYrr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMPSYrr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
def Zn4WriteVPERMYri : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 6;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
def Zn4WriteVPERMPDYmi : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMYri.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMYri.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
def Zn4WriteVPERMDYrr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 5;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMDYrr], (instrs VPERMDYrr)>;
def Zn4WriteVPERMYm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMDYrr.Latency);
- let ReleaseAtCycles = [1, 1, 2];
+ let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMDYrr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
@@ -1446,14 +1446,14 @@ defm : Zn4WriteResInt<WriteFence, [Zn4ALU0123], 1, [100], 1>;
def Zn4WriteLFENCE : SchedWriteRes<[Zn4LSU]> {
let Latency = 1;
- let ReleaseAtCycles = [30];
+ let ResourceCycles = [30];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteLFENCE], (instrs LFENCE)>;
def Zn4WriteSFENCE : SchedWriteRes<[Zn4LSU]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSFENCE], (instrs SFENCE)>;
@@ -1468,7 +1468,7 @@ defm : Zn4WriteResInt<WriteNop, [Zn4ALU0123], 0, [1], 1>; // FIXME: latency not
def Zn4WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
@@ -1477,7 +1477,7 @@ def : InstRW<[Zn4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
def Zn4WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
- let ReleaseAtCycles = [];
+ let ResourceCycles = [];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
@@ -1535,7 +1535,7 @@ def : IsOptimizableRegisterMove<[
// FIXUP and RANGE Instructions
def Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr : SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
@@ -1547,7 +1547,7 @@ def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
// SCALE & REDUCE instructions
def Zn4WriteSCALErr: SchedWriteRes<[Zn4FPFMisc23]> {
let Latency = 6;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSCALErr], (instregex
@@ -1558,7 +1558,7 @@ def : InstRW<[Zn4WriteSCALErr], (instregex
//BF16PS Instructions
def Zn4WriteBF16: SchedWriteRes<[Zn4FPFMisc23]> {
let Latency = 6;
- let ReleaseAtCycles = [6];
+ let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteBF16], (instregex
@@ -1568,7 +1568,7 @@ def : InstRW<[Zn4WriteBF16], (instregex
// BUSD and VPMADD Instructions
def Zn4WriteBUSDr_VPMADDr: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex
@@ -1579,7 +1579,7 @@ def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex
// SHIFT instructions
def Zn4WriteSHIFTrr: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHIFTrr], (instregex
@@ -1596,7 +1596,7 @@ def : InstRW<[Zn4WriteSHIFTrr], (instregex
def Zn4WriteSHIFTri: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 1;
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHIFTri], (instregex
@@ -1606,7 +1606,7 @@ def : InstRW<[Zn4WriteSHIFTri], (instregex
// ALIGN Instructions
def Zn4WriteALIGN: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteALIGN], (instregex
@@ -1616,7 +1616,7 @@ def : InstRW<[Zn4WriteALIGN], (instregex
//PACK Instructions
def Zn4WritePACK: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePACK], (instregex
@@ -1626,7 +1626,7 @@ def : InstRW<[Zn4WritePACK], (instregex
// MAX and MIN Instructions
def Zn4WriteFCmp64: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteFCmp64], (instregex
@@ -1639,7 +1639,7 @@ def : InstRW<[Zn4WriteFCmp64], (instregex
// MOV Instructions
def Zn4MOVS: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVS], (instregex
@@ -1652,7 +1652,7 @@ def : InstRW<[Zn4MOVS], (instregex
def Zn4MOVSZ: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVSZ], (instregex
@@ -1661,7 +1661,7 @@ def : InstRW<[Zn4MOVSZ], (instregex
def Zn4MOVSrr: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 5;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVSrr], (instregex
@@ -1672,7 +1672,7 @@ def : InstRW<[Zn4MOVSrr], (instregex
//VPTEST Instructions
def Zn4VPTESTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 3;
- let ReleaseAtCycles = [3];
+ let ResourceCycles = [3];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ128], (instregex
@@ -1681,7 +1681,7 @@ def : InstRW<[Zn4VPTESTZ128], (instregex
def Zn4VPTESTZ256: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 4;
- let ReleaseAtCycles = [4];
+ let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ256], (instregex
@@ -1690,7 +1690,7 @@ def : InstRW<[Zn4VPTESTZ256], (instregex
def Zn4VPTESTZ: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 5;
- let ReleaseAtCycles = [5];
+ let ResourceCycles = [5];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ], (instregex
@@ -1700,7 +1700,7 @@ def : InstRW<[Zn4VPTESTZ], (instregex
// CONFLICT Instructions
def Zn4CONFLICTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4CONFLICTZ128], (instregex
@@ -1709,7 +1709,7 @@ def : InstRW<[Zn4CONFLICTZ128], (instregex
def Zn4CONFLICTrr: SchedWriteRes<[Zn4FPFMisc01,Zn4FPFMisc12,Zn4FPFMisc23]> {
let Latency = 6;
- let ReleaseAtCycles = [2,2,2];
+ let ResourceCycles = [2,2,2];
let NumMicroOps = 4;
}
def : InstRW<[Zn4CONFLICTrr], (instregex
@@ -1719,7 +1719,7 @@ def : InstRW<[Zn4CONFLICTrr], (instregex
// RSQRT Instructions
def Zn4VRSQRT14PDZ256: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 5;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VRSQRT14PDZ256], (instregex
@@ -1730,7 +1730,7 @@ def : InstRW<[Zn4VRSQRT14PDZ256], (instregex
// PERM Instructions
def Zn4PERMILP: SchedWriteRes<[Zn4FPFMisc123]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMILP], (instregex
@@ -1739,7 +1739,7 @@ def : InstRW<[Zn4PERMILP], (instregex
def Zn4PERMIT2_128: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 3;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_128], (instregex
@@ -1749,7 +1749,7 @@ def : InstRW<[Zn4PERMIT2_128], (instregex
def Zn4PERMIT2_128rr:SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_128rr], (instregex
@@ -1759,7 +1759,7 @@ def : InstRW<[Zn4PERMIT2_128rr], (instregex
def Zn4PERMIT2_256: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 4;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_256], (instregex
@@ -1773,7 +1773,7 @@ def : InstRW<[Zn4PERMIT2_256], (instregex
def Zn4PERMIT2Z: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 5;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2Z], (instregex
@@ -1788,7 +1788,7 @@ def : InstRW<[Zn4PERMIT2Z], (instregex
// ALU SLOW Misc Instructions
def Zn4VecALUZSlow: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
- let ReleaseAtCycles = [2];
+ let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VecALUZSlow], (instrs
diff --git a/llvm/test/TableGen/AcquireAtCycle.td b/llvm/test/TableGen/StartAtCycle.td
similarity index 69%
rename from llvm/test/TableGen/AcquireAtCycle.td
rename to llvm/test/TableGen/StartAtCycle.td
index d9d4ccef547692..d3d642ddf69a91 100644
--- a/llvm/test/TableGen/AcquireAtCycle.td
+++ b/llvm/test/TableGen/StartAtCycle.td
@@ -10,7 +10,7 @@
// RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \
// RUN: FileCheck %s --check-prefix=NEGATIVE_INVALID
-// Make sure that AcquireAtCycle in WriteRes is used to generate the
+// Make sure that StartAtCycle in WriteRes is used to generate the
// correct data.
include "llvm/Target/Target.td"
@@ -44,37 +44,37 @@ def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
// CORRECT-NEXT: { 1, 2, 0}, // #1
// CORRECT-NEXT: { 2, 4, 1}, // #2
// CORRECT-NEXT: { 3, 3, 2}, // #3
- let ReleaseAtCycles = [2, 4, 3];
- let AcquireAtCycles = [0, 1, 2];
+ let ResourceCycles = [2, 4, 3];
+ let StartAtCycles = [0, 1, 2];
}
def : WriteRes<WriteInst_B, [ResX2]> {
-// If unspecified, AcquireAtCycle is set to 0.
+// If unspecified, StartAtCycle is set to 0.
// CORRECT-NEXT: { 3, 1, 0} // #4
- let ReleaseAtCycles = [1];
+ let ResourceCycles = [1];
}
#endif // CORRECT
#ifdef WRONG_SIZE
-// WRONG_SIZE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(AcquireAtCycles) != size(ProcResources): 2 vs 3
+// WRONG_SIZE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(StartAtCycles) != size(ProcResources): 2 vs 3
def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
- let ReleaseAtCycles = [2, 4, 3];
- let AcquireAtCycles = [0, 1];
+ let ResourceCycles = [2, 4, 3];
+ let StartAtCycles = [0, 1];
}
#endif
#ifdef WRONG_VALUE
-// WRONG_VALUE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: AcquireAtCycles < ReleaseAtCycles must hold
+// WRONG_VALUE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: StartAtCycles < Cycles must hold
def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
- let ReleaseAtCycles = [2, 4, 3];
- let AcquireAtCycles = [0, 1, 8];
+ let ResourceCycles = [2, 4, 3];
+ let StartAtCycles = [0, 1, 8];
}
#endif
#ifdef NEGATIVE_INVALID
-// NEGATIVE_INVALID: AcquireAtCycle.td:[[@LINE+1]]:1: error: Invalid value: AcquireAtCycle must be a non-negative value.
+// NEGATIVE_INVALID: StartAtCycle.td:[[@LINE+1]]:1: error: Invalid value: StartAtCycle must be a non-negative value.
def : WriteRes<WriteInst_A, [ResX0]> {
- let ReleaseAtCycles = [2];
- let AcquireAtCycles = [-1];
+ let ResourceCycles = [2];
+ let StartAtCycles = [-1];
}
#endif
diff --git a/llvm/tools/llvm-exegesis/lib/Analysis.cpp b/llvm/tools/llvm-exegesis/lib/Analysis.cpp
index bd088b907aaf7d..7c443732c2c0f2 100644
--- a/llvm/tools/llvm-exegesis/lib/Analysis.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Analysis.cpp
@@ -390,7 +390,7 @@ void Analysis::printSchedClassDescHtml(const ResolvedSchedClass &RSC,
OS << "<li><span class=\"mono\">";
writeEscaped<kEscapeHtml>(OS,
SM.getProcResource(WPR.ProcResourceIdx)->Name);
- OS << "</span>: " << WPR.ReleaseAtCycle << "</li>";
+ OS << "</span>: " << WPR.Cycles << "</li>";
}
OS << "</ul></td>";
// Idealized port pressure.
diff --git a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
index 08fd7184068c3b..6b768c8e08288e 100644
--- a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
@@ -83,20 +83,19 @@ getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
const MCWriteProcResEntry *WPR = Entry.second;
const MCProcResourceDesc *const ProcResDesc =
SM.getProcResource(WPR->ProcResourceIdx);
- // TODO: Handle AcquireAtAtCycle in llvm-exegesis and llvm-mca. See
+ // TODO: Handle StartAtCycle in llvm-exegesis and llvm-mca. See
// https://github.com/llvm/llvm-project/issues/62680 and
// https://github.com/llvm/llvm-project/issues/62681
- assert(WPR->AcquireAtCycle == 0 &&
- "`llvm-exegesis` does not handle AcquireAtCycle > 0");
+ assert(WPR->StartAtCycle == 0 &&
+ "`llvm-exegesis` does not handle StartAtCycle > 0");
if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
// This is a ProcResUnit.
- Result.push_back(
- {WPR->ProcResourceIdx, WPR->ReleaseAtCycle, WPR->AcquireAtCycle});
- ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->ReleaseAtCycle;
+ Result.push_back({WPR->ProcResourceIdx, WPR->Cycles, WPR->StartAtCycle});
+ ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles;
} else {
// This is a ProcResGroup. First see if it contributes any cycles or if
// it has cycles just from subunits.
- float RemainingCycles = WPR->ReleaseAtCycle;
+ float RemainingCycles = WPR->Cycles;
for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
++SubResIdx) {
@@ -109,7 +108,7 @@ getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
// The ProcResGroup contributes `RemainingCycles` cycles of its own.
Result.push_back({WPR->ProcResourceIdx,
static_cast<uint16_t>(std::round(RemainingCycles)),
- WPR->AcquireAtCycle});
+ WPR->StartAtCycle});
// Spread the remaining cycles over all subunits.
for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
@@ -214,13 +213,13 @@ computeIdealizedProcResPressure(const MCSchedModel &SM,
SM.getProcResource(WPR.ProcResourceIdx);
if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
// This is a ProcResUnit.
- DensePressure[WPR.ProcResourceIdx] += WPR.ReleaseAtCycle;
+ DensePressure[WPR.ProcResourceIdx] += WPR.Cycles;
} else {
// This is a ProcResGroup.
SmallVector<uint16_t, 32> Subunits(ProcResDesc->SubUnitsIdxBegin,
ProcResDesc->SubUnitsIdxBegin +
ProcResDesc->NumUnits);
- distributePressure(WPR.ReleaseAtCycle, Subunits, DensePressure);
+ distributePressure(WPR.Cycles, Subunits, DensePressure);
}
}
// Turn dense pressure into sparse pressure by removing zero entries.
diff --git a/llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp b/llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
index b702113b39617a..b254ccd6670ffb 100644
--- a/llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
+++ b/llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
@@ -611,9 +611,9 @@ void BottleneckAnalysis::printBottleneckHints(raw_ostream &OS) const {
ArrayRef<unsigned> Distribution = Tracker.getResourcePressureDistribution();
const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
for (unsigned I = 0, E = Distribution.size(); I < E; ++I) {
- unsigned ReleaseAtCycles = Distribution[I];
- if (ReleaseAtCycles) {
- double Frequency = (double)ReleaseAtCycles * 100 / TotalCycles;
+ unsigned ResourceCycles = Distribution[I];
+ if (ResourceCycles) {
+ double Frequency = (double)ResourceCycles * 100 / TotalCycles;
const MCProcResourceDesc &PRDesc = *SM.getProcResource(I);
OS << "\n - " << PRDesc.Name << " [ "
<< format("%.2f", floor((Frequency * 100) + 0.5) / 100) << "% ]";
diff --git a/llvm/tools/llvm-mca/Views/ResourcePressureView.cpp b/llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
index f39350f3b45852..0f059bcc0a0698 100644
--- a/llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
+++ b/llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
@@ -54,7 +54,7 @@ void ResourcePressureView::onEvent(const HWInstructionEvent &Event) {
const auto &IssueEvent = static_cast<const HWInstructionIssuedEvent &>(Event);
ArrayRef<llvm::MCInst> Source = getSource();
const unsigned SourceIdx = Event.IR.getSourceIndex() % Source.size();
- for (const std::pair<ResourceRef, ReleaseAtCycles> &Use :
+ for (const std::pair<ResourceRef, ResourceCycles> &Use :
IssueEvent.UsedResources) {
const ResourceRef &RR = Use.first;
assert(Resource2VecIndex.contains(RR.first));
@@ -181,7 +181,7 @@ json::Value ResourcePressureView::toJSON() const {
ArrayRef<llvm::MCInst> Source = getSource();
const unsigned Executions = LastInstructionIdx / Source.size() + 1;
for (const auto &R : enumerate(ResourceUsage)) {
- const ReleaseAtCycles &RU = R.value();
+ const ResourceCycles &RU = R.value();
if (RU.getNumerator() == 0)
continue;
unsigned InstructionIndex = R.index() / NumResourceUnits;
diff --git a/llvm/tools/llvm-mca/Views/ResourcePressureView.h b/llvm/tools/llvm-mca/Views/ResourcePressureView.h
index be8ad04102fd05..c3993a08c170ab 100644
--- a/llvm/tools/llvm-mca/Views/ResourcePressureView.h
+++ b/llvm/tools/llvm-mca/Views/ResourcePressureView.h
@@ -78,7 +78,7 @@ class ResourcePressureView : public InstructionView {
llvm::DenseMap<unsigned, unsigned> Resource2VecIndex;
// Table of resources used by instructions.
- std::vector<ReleaseAtCycles> ResourceUsage;
+ std::vector<ResourceCycles> ResourceUsage;
unsigned NumResourceUnits;
void printResourcePressurePerIter(llvm::raw_ostream &OS) const;
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 0cc1b61768b5f8..e4eb23649e9623 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -119,8 +119,8 @@ class SubtargetEmitter {
const CodeGenProcModel &ProcModel);
Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
const CodeGenProcModel &ProcModel);
- void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
- std::vector<int64_t> &AcquireAtCycles,
+ void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
+ std::vector<int64_t> &StartAtCycles,
const CodeGenProcModel &ProcModel);
void GenSchedClassTables(const CodeGenProcModel &ProcModel,
SchedClassTables &SchedTables);
@@ -976,10 +976,11 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
// Expand an explicit list of processor resources into a full list of implied
// resource groups and super resources that cover them.
-void SubtargetEmitter::ExpandProcResources(
- RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
- std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
- assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
+void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
+ std::vector<int64_t> &Cycles,
+ std::vector<int64_t> &StartAtCycles,
+ const CodeGenProcModel &PM) {
+ assert(PRVec.size() == Cycles.size() && "failed precondition");
for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
Record *PRDef = PRVec[i];
RecVec SubResources;
@@ -999,8 +1000,8 @@ void SubtargetEmitter::ExpandProcResources(
SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM,
SubDef->getLoc());
PRVec.push_back(SuperDef);
- ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
- AcquireAtCycles.push_back(AcquireAtCycles[i]);
+ Cycles.push_back(Cycles[i]);
+ StartAtCycles.push_back(StartAtCycles[i]);
SubDef = SuperDef;
}
}
@@ -1016,8 +1017,8 @@ void SubtargetEmitter::ExpandProcResources(
}
if (SubI == SubE) {
PRVec.push_back(PR);
- ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
- AcquireAtCycles.push_back(AcquireAtCycles[i]);
+ Cycles.push_back(Cycles[i]);
+ StartAtCycles.push_back(StartAtCycles[i]);
}
}
}
@@ -1149,69 +1150,67 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// Create an entry for each ProcResource listed in WriteRes.
RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
- std::vector<int64_t> ReleaseAtCycles =
- WriteRes->getValueAsListOfInts("ReleaseAtCycles");
+ std::vector<int64_t> Cycles =
+ WriteRes->getValueAsListOfInts("ResourceCycles");
- std::vector<int64_t> AcquireAtCycles =
- WriteRes->getValueAsListOfInts("AcquireAtCycles");
+ std::vector<int64_t> StartAtCycles =
+ WriteRes->getValueAsListOfInts("StartAtCycles");
// Check consistency of the two vectors carrying the start and
// stop cycles of the resources.
- if (!ReleaseAtCycles.empty() &&
- ReleaseAtCycles.size() != PRVec.size()) {
- // If ReleaseAtCycles is provided, check consistency.
+ if (!Cycles.empty() && Cycles.size() != PRVec.size()) {
+ // If ResourceCycles is provided, check consistency.
PrintFatalError(
WriteRes->getLoc(),
- Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "
+ Twine("Inconsistent resource cycles: size(ResourceCycles) != "
"size(ProcResources): ")
.concat(Twine(PRVec.size()))
.concat(" vs ")
- .concat(Twine(ReleaseAtCycles.size())));
+ .concat(Twine(Cycles.size())));
}
- if (!AcquireAtCycles.empty() && AcquireAtCycles.size() != PRVec.size()) {
+ if (!StartAtCycles.empty() && StartAtCycles.size() != PRVec.size()) {
PrintFatalError(
WriteRes->getLoc(),
- Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "
+ Twine("Inconsistent resource cycles: size(StartAtCycles) != "
"size(ProcResources): ")
- .concat(Twine(AcquireAtCycles.size()))
+ .concat(Twine(StartAtCycles.size()))
.concat(" vs ")
.concat(Twine(PRVec.size())));
}
- if (ReleaseAtCycles.empty()) {
- // If ReleaseAtCycles is not provided, default to one cycle
+ if (Cycles.empty()) {
+ // If ResourceCycles is not provided, default to one cycle
// per resource.
- ReleaseAtCycles.resize(PRVec.size(), 1);
+ Cycles.resize(PRVec.size(), 1);
}
- if (AcquireAtCycles.empty()) {
- // If AcquireAtCycles is not provided, reserve the resource
+ if (StartAtCycles.empty()) {
+ // If StartAtCycles is not provided, reserve the resource
// starting from cycle 0.
- AcquireAtCycles.resize(PRVec.size(), 0);
+ StartAtCycles.resize(PRVec.size(), 0);
}
- assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
+ assert(StartAtCycles.size() == Cycles.size());
- ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
- assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
+ ExpandProcResources(PRVec, Cycles, StartAtCycles, ProcModel);
+ assert(StartAtCycles.size() == Cycles.size());
for (unsigned PRIdx = 0, PREnd = PRVec.size();
PRIdx != PREnd; ++PRIdx) {
MCWriteProcResEntry WPREntry;
WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
- WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];
- WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];
- if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {
- PrintFatalError(
- WriteRes->getLoc(),
- Twine("Inconsistent resource cycles: AcquireAtCycles "
- "< ReleaseAtCycles must hold."));
+ WPREntry.Cycles = Cycles[PRIdx];
+ WPREntry.StartAtCycle = StartAtCycles[PRIdx];
+ if (StartAtCycles[PRIdx] > Cycles[PRIdx]) {
+ PrintFatalError(WriteRes->getLoc(),
+ Twine("Inconsistent resource cycles: StartAtCycles "
+ "< Cycles must hold."));
}
- if (AcquireAtCycles[PRIdx] < 0) {
+ if (StartAtCycles[PRIdx] < 0) {
PrintFatalError(WriteRes->getLoc(),
- Twine("Invalid value: AcquireAtCycle "
+ Twine("Invalid value: StartAtCycle "
"must be a non-negative value."));
}
// If this resource is already used in this sequence, add the current
@@ -1229,10 +1228,9 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// `SubtargetEmitter::EmitSchedClassTables`), or
// 2. thinking how to merge multiple intervals into a
// single interval.
- assert(WPREntry.AcquireAtCycle == 0 &&
+ assert(WPREntry.StartAtCycle == 0 &&
"multiple use ofthe same resource is not yet handled");
- WriteProcResources[WPRIdx].ReleaseAtCycle +=
- WPREntry.ReleaseAtCycle;
+ WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
break;
}
}
@@ -1336,7 +1334,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
raw_ostream &OS) {
// Emit global WriteProcResTable.
- OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
+ OS << "\n// {ProcResourceIdx, Cycles, StartAtCycle}\n"
<< "extern const llvm::MCWriteProcResEntry " << Target
<< "WriteProcResTable[] = {\n"
<< " { 0, 0, 0 }, // Invalid\n";
@@ -1344,8 +1342,8 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
WPRIdx != WPREnd; ++WPRIdx) {
MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
- << format("%2d", WPREntry.ReleaseAtCycle) << ", "
- << format("%2d", WPREntry.AcquireAtCycle) << "}";
+ << format("%2d", WPREntry.Cycles) << ", "
+ << format("%2d", WPREntry.StartAtCycle) << "}";
if (WPRIdx + 1 < WPREnd)
OS << ',';
OS << " // #" << WPRIdx << '\n';
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