[PATCH] D158195: [RISCV] Combine (vrot{l,r} vxi16, 8) -> vrev8

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 551964.
luke marked an inline comment as done.
luke added a comment.

Since these rotates are only emitted in one place during lowering, remove the combine and just 
handle it there.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158195/new/

https://reviews.llvm.org/D158195

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -202,13 +202,13 @@
 ; ZVBB_V-LABEL: shuffle_v8i8_as_i16:
 ; ZVBB_V:       # %bb.0:
 ; ZVBB_V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB_V-NEXT:    vror.vi v8, v8, 8
+; ZVBB_V-NEXT:    vrev8.v v8, v8
 ; ZVBB_V-NEXT:    ret
 ;
 ; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i16:
 ; ZVBB_ZVE32X:       # %bb.0:
 ; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e16, m2, ta, ma
-; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 8
+; ZVBB_ZVE32X-NEXT:    vrev8.v v8, v8
 ; ZVBB_ZVE32X-NEXT:    ret
   %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
   ret <8 x i8> %shuffle
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -180,7 +180,7 @@
 ; ZVBB-LABEL: reverse_v2i8:
 ; ZVBB:       # %bb.0:
 ; ZVBB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT:    vror.vi v8, v8, 8
+; ZVBB-NEXT:    vrev8.v v8, v8
 ; ZVBB-NEXT:    ret
   %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
   ret <2 x i8> %res
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4201,15 +4201,22 @@
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, RotateVT, Subtarget);
   SDValue VL =
       getDefaultVLOps(RotateVT, ContainerVT, DL, DAG, Subtarget).second;
-  SDValue RotateAmtSplat = DAG.getNode(
-      RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
-      DAG.getConstant(RotateAmt, DL, Subtarget.getXLenVT()), VL);
-  RotateAmtSplat =
-      convertFromScalableVector(RotateVT, RotateAmtSplat, DAG, Subtarget);
+  SDValue Op = DAG.getBitcast(RotateVT, SVN->getOperand(0));
+
+  SDValue Rotate;
+  // A rotate of an i16 by 8 bits either direction is equivalent to a byteswap,
+  // so canonicalize to vrev8.
+  if (RotateVT.getScalarType() == MVT::i16 && RotateAmt == 8) {
+    Rotate = DAG.getNode(ISD::BSWAP, DL, RotateVT, Op);
+  } else {
+    SDValue RotateAmtSplat = DAG.getNode(
+        RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
+        DAG.getConstant(RotateAmt, DL, Subtarget.getXLenVT()), VL);
+    RotateAmtSplat =
+        convertFromScalableVector(RotateVT, RotateAmtSplat, DAG, Subtarget);
+    Rotate = DAG.getNode(ISD::ROTL, DL, RotateVT, Op, RotateAmtSplat);
+  }
 
-  SDValue Rotate =
-      DAG.getNode(ISD::ROTL, DL, RotateVT,
-                  DAG.getBitcast(RotateVT, SVN->getOperand(0)), RotateAmtSplat);
   return DAG.getBitcast(VT, Rotate);
 }
 


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