[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, nikic.
Herald added subscribers: StephenFan, pengfei, hiraditya.
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Extension to the signbit case, if the signbits extend down through all the demanded bits then SMIN/SMAX nodes can be simplified to a OR/AND.

Alive2: https://alive2.llvm.org/ce/z/StSehz


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158364

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/known-signbits-vector.ll

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