[PATCH] D157272: [RISCV] Handle subregs when folding vmerge into vops

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.
Herald added a subscriber: sunshaoce.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3354
+  // TargetConstant:i32<4>
+  //   t40: v2i32 = COPY_TO_REGCLASS t41, TargetConstant:i64<22>
+  //     t41: nxv1i32,ch = PseudoVLE32_V_MF2 ...
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luke wrote:
> reames wrote:
> > I'm looking at this, and am trying to understand why we get the COPY_TO_REGCLASS here.  If I'm reading this right, we should be generating this only when doing a insert_subreg between two equally LMUL-sized register groups.  Given that, I think we must have had two insert_subregs originally, and shouldn't one of have been combined away?
> IIUC we generate COPY_TO_REGCLASSes when doing either an or insert_subvector extract_subvector between two equally LMUL-sized register groups.
> The input graph before isel seems to have both an insert_subvector and extract_subvector, is that the bit that you're saying should be combined?
> 
> ```
>   t0: ch,glue = EntryToken
>       t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
>             t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
>             t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
>             t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
>           t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
>         t25: v4i32 = extract_subvector t24, Constant:i64<0>
>       t26: nxv4i32 = insert_subvector undef:nxv4i32, t25, Constant:i64<0>
>       t28: nxv4i1 = RISCVISD::VMSET_VL Constant:i64<8>
>     t30: nxv4i32 = RISCVISD::VSLIDEUP_VL t2, t26, Constant:i64<4>, t28, Constant:i64<8>, TargetConstant:i64<1>
>   t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
>   t19: ch = RISCVISD::RET_GLUE t18, Register:nxv4i32 $v8m2, t18:1
> ```
> 
> The insert_subvector gets selected as an INSERT_SUBREG:
> 
> ```
>   t0: ch,glue = EntryToken
>       t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
>             t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
>             t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
>             t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
>           t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
>         t25: v4i32 = extract_subvector t24, Constant:i64<0>
>       t36: nxv4i32 = INSERT_SUBREG undef:nxv4i32, t25, TargetConstant:i32<4>
>     t30: nxv4i32 = PseudoVSLIDEUP_VI_M2 t2, t36, TargetConstant:i64<4>, TargetConstant:i64<8>, TargetConstant:i64<5>, TargetConstant:i64<1>
>   t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
>   t37: i64 = TargetConstant<20>
>   t19: ch = PseudoRET Register:nxv4i32 $v8m2, t18, t18:1
> ```
> 
> And then the extract_subvector gets selected as a COPY_TO_REGCLASS
> 
> ```
>   t0: ch,glue = EntryToken
>       t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
>             t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
>             t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
>             t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
>           t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
>         t38: v4i32 = COPY_TO_REGCLASS t24, TargetConstant:i64<20>
>       t36: nxv4i32 = INSERT_SUBREG undef:nxv4i32, t38, TargetConstant:i32<4>
>     t30: nxv4i32 = PseudoVSLIDEUP_VI_M2 t2, t36, TargetConstant:i64<4>, TargetConstant:i64<8>, TargetConstant:i64<5>, TargetConstant:i64<1>
>   t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
>   t19: ch = PseudoRET Register:nxv4i32 $v8m2, t18, t18:1
> ```
https://reviews.llvm.org/D158201 should improve this.  Not sure it entirely resolves the need for the COPY_TO_REGCLASS, but it at least picks up the redundant pair.  


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157272/new/

https://reviews.llvm.org/D157272