[PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 17 09:07:18 PDT 2023

Previous message: [PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion
Next message: [PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158086/new/

https://reviews.llvm.org/D158086

Previous message: [PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion
Next message: [PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list