[PATCH] D157113: [AArch64] Support more types for ZEXT/SEXT with Global Isel

[Tuan Chuong Goh via Phabricator via llvm-commits]

chuongg3 updated this revision to Diff 550738.
chuongg3 marked 2 inline comments as done.
chuongg3 added a comment.

Rectified comments made by aemerson
Instructions are built using register types instead of creating a register for the instruction to be built


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157113/new/

https://reviews.llvm.org/D157113

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/sext.ll
  llvm/test/CodeGen/AArch64/zext.ll

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