[PATCH] D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

There is a problem here, can someone explain it?

For LLVM IR:
`reduced.ll`

  @g = external global [4000 x i32], align 4
  define void @test() nounwind {
    call void asm "sw zero, $0", "=*m"(ptr elementtype(i32) @g)
    ret void
  }

`llc -code-model=medium -no-integrated-as reduced.ll`

  test:                                   # @test
  # %bb.0:
  .Lpcrel_hi0:
  	auipc	a0, %pcrel_hi(g)
  	#APP
  	sw zero, %pcrel_lo(.Lpcrel_hi0)(a0)
  	#NO_APP
  	ret

`llc -code-model=medium reduced.ll`

  test:                                   # @test
  # %bb.0:
  .Lpcrel_hi0:
  	auipc	a0, %pcrel_hi(g)
  	#APP
  	sw	zero, %pcrel_lo(.Lpcrel_hi00)(a0)
  	#NO_APP
  	ret

The difference is that there is an extra `0` after `.Lpcrel_hi` when there is no `-no-integrated-as`.
Is this a bug or a feature by design?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158062/new/

https://reviews.llvm.org/D158062