[PATCH] D157588: [RISCV] Add overlapping constraints label

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2906
 
 multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
   foreach m = MxListW in {
----------------
Is this class unused? I would expect it to need a TargetConstaintType


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2912
 
-multiclass VPseudoVWMUL_VV_VX {
+multiclass VPseudoVWMUL_VV_VX<int TargetConstraintType = 1> {
   foreach m = MxListW in {
----------------
Can we default to 3 and remove from instantiation?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2924
 
-multiclass VPseudoVWMUL_VV_VF_RM {
+multiclass VPseudoVWMUL_VV_VF_RM<int TargetConstraintType = 1> {
   foreach m = MxListFW in {
----------------
This class is used once. Can we default the constraint type to 3 and remove from the instantiation?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2940
 
-multiclass VPseudoVWALU_WV_WX {
+multiclass VPseudoVWALU_WV_WX<int TargetConstraintType = 1> {
   foreach m = MxListW in {
----------------
Can we default all the VW classes to 3? May even just default at VPseudoBinaryW_WV?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157588/new/

https://reviews.llvm.org/D157588