[PATCH] D156909: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 14 13:01:35 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa63bd7e99b00: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands (authored by reames).
Changed prior to commit:
https://reviews.llvm.org/D156909?vs=549998&id=550059#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D156909/new/
https://reviews.llvm.org/D156909
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O0-pipeline.ll
llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/cross-block-cse.ll
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
llvm/test/CodeGen/RISCV/rvv/stepvector.ll
llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpload.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpstore.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
More information about the llvm-commits
mailing list