[PATCH] D157517: [AArch64][SVE] Add asm predicate constraint Uph

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a subscriber: rsandifo-arm.
sdesmalen added a comment.

FYI @rsandifo-arm



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Comment at: llvm/docs/LangRef.rst:4997
 - ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive.
+- ``Uph``: One of the high eight SVE predicate registers (P8 to P15)
 - ``Upl``: One of the low eight SVE predicate registers (P0 to P7)
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nit: upper


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Comment at: llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll:78
+; CHECK: INLINEASM {{.*}} [[ARG4]]
+define <vscale x 8 x half> @foofoo(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
+  %1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w, at 3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
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nit: can you find a more appropriate name?


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https://reviews.llvm.org/D157517