[llvm] b560d5c - [CodeGen] Pre-commit tests showing incorrect pattern FMLA_* pseudo instructions

[Igor Kirillov via llvm-commits]

Author: Igor Kirillov
Date: 2023-08-08T10:52:55Z
New Revision: b560d5c7e380c1c412b892a3e22f8ee15a522381

URL: https://github.com/llvm/llvm-project/commit/b560d5c7e380c1c412b892a3e22f8ee15a522381
DIFF: https://github.com/llvm/llvm-project/commit/b560d5c7e380c1c412b892a3e22f8ee15a522381.diff

LOG: [CodeGen] Pre-commit tests showing incorrect pattern FMLA_* pseudo instructions

Differential Revision: https://reviews.llvm.org/D157094

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/sve-fp-combine.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
index ef68f8e7eeca96..87562b49f84b66 100644
--- a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
@@ -1267,3 +1267,37 @@ define <vscale x 4 x float> @fadd_sel_fmul_no_contract_s(<vscale x 4 x float> %a
   %fadd = fadd nsz <vscale x 4 x float> %a, %sel
   ret <vscale x 4 x float> %fadd
 }
+
+define <vscale x 8 x half> @fma_sel_h_
diff erent_arg_order(<vscale x 8 x i1> %pred, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2, <vscale x 8 x half> %acc) {
+; CHECK-LABEL: fma_sel_h_
diff erent_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %m1, <vscale x 8 x half> %m2, <vscale x 8 x half> %acc)
+  %masked.mul.add = select <vscale x 8 x i1> %pred, <vscale x 8 x half> %mul.add, <vscale x 8 x half> %acc
+  ret <vscale x 8 x half> %masked.mul.add
+}
+
+define <vscale x 4 x float> @fma_sel_s_
diff erent_arg_order(<vscale x 4 x i1> %pred, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2, <vscale x 4 x float> %acc) {
+; CHECK-LABEL: fma_sel_s_
diff erent_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %m1, <vscale x 4 x float> %m2, <vscale x 4 x float> %acc)
+  %masked.mul.add = select <vscale x 4 x i1> %pred, <vscale x 4 x float> %mul.add, <vscale x 4 x float> %acc
+  ret <vscale x 4 x float> %masked.mul.add
+}
+
+define <vscale x 2 x double> @fma_sel_d_
diff erent_arg_order(<vscale x 2 x i1> %pred, <vscale x 2 x double> %m1, <vscale x 2 x double> %m2, <vscale x 2 x double> %acc) {
+; CHECK-LABEL: fma_sel_d_
diff erent_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %m1, <vscale x 2 x double> %m2, <vscale x 2 x double> %acc)
+  %masked.mul.add = select <vscale x 2 x i1> %pred, <vscale x 2 x double> %mul.add, <vscale x 2 x double> %acc
+  ret <vscale x 2 x double> %masked.mul.add
+}
+
+declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)