[PATCH] D153848: [RISCV] Apply promotion for f16 vector ops when only have zvfhmin.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 548100.
jacquesguan added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153848/new/

https://reviews.llvm.org/D153848

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll