[PATCH] D157117: [RISCV] Use vmerge for INSERT_VECTOR_ELT w/small constant indices

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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Currently, we default to using a vmv.s.x and vslide1up sequence for inserting elements into a vector.  This lowering has a couple of downsides.  First, it requires a temporary register to hold the scalar-as-vector.  Second, for inserts into the middle of a vector, the VL chosen needs to be Idx + 1.  This causes VL toggles since these odd VLs are unlikely to be sharable.

Instead, we can use a vmerge.vx to perform the insert.  This avoids the need for the temporary register and odd VLs, but requires the population of a mask register.  For the moment, restrict usage to when we can use a single vmv.v.i to populate the mask - i.e. indices less than 5.  If we like the direction of this patch, this restriction can be lifted by using a vmseq(vid, index) sequence, but I'll defer that to later work.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157117

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

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