[llvm] c1c5da8 - [RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 20:20:51 PDT 2023
Author: Craig Topper
Date: 2023-08-02T20:16:50-07:00
New Revision: c1c5da8f1f053ea76ef7111904cd33732e21b7ac
URL: https://github.com/llvm/llvm-project/commit/c1c5da8f1f053ea76ef7111904cd33732e21b7ac
DIFF: https://github.com/llvm/llvm-project/commit/c1c5da8f1f053ea76ef7111904cd33732e21b7ac.diff
LOG: [RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
fp-imm.ll and zfh-imm.ll test 0.0 and -0.0 while float/double/half-imm.ll
tested other non-zero constants. It seems like they should all be
tested together.
There are slight coverage changes due to different command lines,
but I'm not sure its meaningful. For example, we now don't test
double 0.0 and -0.0 with only the F extension.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D156929
Added:
Modified:
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/float-imm.ll
llvm/test/CodeGen/RISCV/half-imm.ll
Removed:
llvm/test/CodeGen/RISCV/fp-imm.ll
llvm/test/CodeGen/RISCV/zfh-imm.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 3f7a14b2cefded..dd554a8ce0dcf7 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -66,3 +66,32 @@ define double @double_imm_op(double %a) nounwind {
%1 = fadd double %a, 1.0
ret double %1
}
+
+define double @double_positive_zero(ptr %pd) nounwind {
+; CHECKRV32ZDINX-LABEL: double_positive_zero:
+; CHECKRV32ZDINX: # %bb.0:
+; CHECKRV32ZDINX-NEXT: li a0, 0
+; CHECKRV32ZDINX-NEXT: li a1, 0
+; CHECKRV32ZDINX-NEXT: ret
+;
+; CHECKRV64ZDINX-LABEL: double_positive_zero:
+; CHECKRV64ZDINX: # %bb.0:
+; CHECKRV64ZDINX-NEXT: li a0, 0
+; CHECKRV64ZDINX-NEXT: ret
+ ret double 0.0
+}
+
+define double @double_negative_zero(ptr %pd) nounwind {
+; CHECKRV32ZDINX-LABEL: double_negative_zero:
+; CHECKRV32ZDINX: # %bb.0:
+; CHECKRV32ZDINX-NEXT: lui a1, 524288
+; CHECKRV32ZDINX-NEXT: li a0, 0
+; CHECKRV32ZDINX-NEXT: ret
+;
+; CHECKRV64ZDINX-LABEL: double_negative_zero:
+; CHECKRV64ZDINX: # %bb.0:
+; CHECKRV64ZDINX-NEXT: li a0, -1
+; CHECKRV64ZDINX-NEXT: slli a0, a0, 63
+; CHECKRV64ZDINX-NEXT: ret
+ ret double -0.0
+}
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
index a99ba3faa5768c..a25955e2ef349f 100644
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -46,3 +46,31 @@ define float @float_imm_op(float %a) nounwind {
%1 = fadd float %a, 1.0
ret float %1
}
+
+define float @float_positive_zero(ptr %pf) nounwind {
+; CHECK-LABEL: float_positive_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.w.x fa0, zero
+; CHECK-NEXT: ret
+;
+; CHECKZFINX-LABEL: float_positive_zero:
+; CHECKZFINX: # %bb.0:
+; CHECKZFINX-NEXT: li a0, 0
+; CHECKZFINX-NEXT: ret
+ ret float 0.0
+}
+
+define float @float_negative_zero(ptr %pf) nounwind {
+; CHECK-LABEL: float_negative_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: fmv.w.x fa0, a0
+; CHECK-NEXT: ret
+;
+; CHECKZFINX-LABEL: float_negative_zero:
+; CHECKZFINX: # %bb.0:
+; CHECKZFINX-NEXT: lui a0, 524288
+; CHECKZFINX-NEXT: ret
+ ret float -0.0
+}
+
diff --git a/llvm/test/CodeGen/RISCV/fp-imm.ll b/llvm/test/CodeGen/RISCV/fp-imm.ll
deleted file mode 100644
index e7b2e62b2f6c67..00000000000000
--- a/llvm/test/CodeGen/RISCV/fp-imm.ll
+++ /dev/null
@@ -1,110 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
-; RUN: | FileCheck --check-prefix=RV32F %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
-; RUN: | FileCheck --check-prefix=RV32D %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
-; RUN: | FileCheck --check-prefix=RV64F %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
-; RUN: | FileCheck --check-prefix=RV64D %s
-
-define float @f32_positive_zero(ptr %pf) nounwind {
-; RV32F-LABEL: f32_positive_zero:
-; RV32F: # %bb.0:
-; RV32F-NEXT: fmv.w.x fa0, zero
-; RV32F-NEXT: ret
-;
-; RV32D-LABEL: f32_positive_zero:
-; RV32D: # %bb.0:
-; RV32D-NEXT: fmv.w.x fa0, zero
-; RV32D-NEXT: ret
-;
-; RV64F-LABEL: f32_positive_zero:
-; RV64F: # %bb.0:
-; RV64F-NEXT: fmv.w.x fa0, zero
-; RV64F-NEXT: ret
-;
-; RV64D-LABEL: f32_positive_zero:
-; RV64D: # %bb.0:
-; RV64D-NEXT: fmv.w.x fa0, zero
-; RV64D-NEXT: ret
- ret float 0.0
-}
-
-define float @f32_negative_zero(ptr %pf) nounwind {
-; RV32F-LABEL: f32_negative_zero:
-; RV32F: # %bb.0:
-; RV32F-NEXT: lui a0, 524288
-; RV32F-NEXT: fmv.w.x fa0, a0
-; RV32F-NEXT: ret
-;
-; RV32D-LABEL: f32_negative_zero:
-; RV32D: # %bb.0:
-; RV32D-NEXT: lui a0, 524288
-; RV32D-NEXT: fmv.w.x fa0, a0
-; RV32D-NEXT: ret
-;
-; RV64F-LABEL: f32_negative_zero:
-; RV64F: # %bb.0:
-; RV64F-NEXT: lui a0, 524288
-; RV64F-NEXT: fmv.w.x fa0, a0
-; RV64F-NEXT: ret
-;
-; RV64D-LABEL: f32_negative_zero:
-; RV64D: # %bb.0:
-; RV64D-NEXT: lui a0, 524288
-; RV64D-NEXT: fmv.w.x fa0, a0
-; RV64D-NEXT: ret
- ret float -0.0
-}
-
-define double @f64_positive_zero(ptr %pd) nounwind {
-; RV32F-LABEL: f64_positive_zero:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 0
-; RV32F-NEXT: li a1, 0
-; RV32F-NEXT: ret
-;
-; RV32D-LABEL: f64_positive_zero:
-; RV32D: # %bb.0:
-; RV32D-NEXT: fcvt.d.w fa0, zero
-; RV32D-NEXT: ret
-;
-; RV64F-LABEL: f64_positive_zero:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 0
-; RV64F-NEXT: ret
-;
-; RV64D-LABEL: f64_positive_zero:
-; RV64D: # %bb.0:
-; RV64D-NEXT: fmv.d.x fa0, zero
-; RV64D-NEXT: ret
- ret double 0.0
-}
-
-define double @f64_negative_zero(ptr %pd) nounwind {
-; RV32F-LABEL: f64_negative_zero:
-; RV32F: # %bb.0:
-; RV32F-NEXT: lui a1, 524288
-; RV32F-NEXT: li a0, 0
-; RV32F-NEXT: ret
-;
-; RV32D-LABEL: f64_negative_zero:
-; RV32D: # %bb.0:
-; RV32D-NEXT: fcvt.d.w fa5, zero
-; RV32D-NEXT: fneg.d fa0, fa5
-; RV32D-NEXT: ret
-;
-; RV64F-LABEL: f64_negative_zero:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, -1
-; RV64F-NEXT: slli a0, a0, 63
-; RV64F-NEXT: ret
-;
-; RV64D-LABEL: f64_negative_zero:
-; RV64D: # %bb.0:
-; RV64D-NEXT: fmv.d.x fa5, zero
-; RV64D-NEXT: fneg.d fa0, fa5
-; RV64D-NEXT: ret
- ret double -0.0
-}
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index 39b4baabc27b27..9c11010540e15d 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -95,3 +95,61 @@ define half @half_imm_op(half %a) nounwind {
%1 = fadd half %a, 1.0
ret half %1
}
+
+define half @half_positive_zero(ptr %pf) nounwind {
+; CHECK-LABEL: half_positive_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x fa0, zero
+; CHECK-NEXT: ret
+;
+; RV32IZHINX-LABEL: half_positive_zero:
+; RV32IZHINX: # %bb.0:
+; RV32IZHINX-NEXT: li a0, 0
+; RV32IZHINX-NEXT: ret
+;
+; RV64IZHINX-LABEL: half_positive_zero:
+; RV64IZHINX: # %bb.0:
+; RV64IZHINX-NEXT: li a0, 0
+; RV64IZHINX-NEXT: ret
+;
+; CHECKIZFHMIN-LABEL: half_positive_zero:
+; CHECKIZFHMIN: # %bb.0:
+; CHECKIZFHMIN-NEXT: fmv.h.x fa0, zero
+; CHECKIZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: half_positive_zero:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: li a0, 0
+; CHECKIZHINXMIN-NEXT: ret
+ ret half 0.0
+}
+
+define half @half_negative_zero(ptr %pf) nounwind {
+; CHECK-LABEL: half_negative_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 1048568
+; CHECK-NEXT: fmv.h.x fa0, a0
+; CHECK-NEXT: ret
+;
+; RV32IZHINX-LABEL: half_negative_zero:
+; RV32IZHINX: # %bb.0:
+; RV32IZHINX-NEXT: lui a0, 1048568
+; RV32IZHINX-NEXT: ret
+;
+; RV64IZHINX-LABEL: half_negative_zero:
+; RV64IZHINX: # %bb.0:
+; RV64IZHINX-NEXT: lui a0, 1048568
+; RV64IZHINX-NEXT: ret
+;
+; CHECKIZFHMIN-LABEL: half_negative_zero:
+; CHECKIZFHMIN: # %bb.0:
+; CHECKIZFHMIN-NEXT: lui a0, 1048568
+; CHECKIZFHMIN-NEXT: fmv.h.x fa0, a0
+; CHECKIZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: half_negative_zero:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: lui a0, 1048568
+; CHECKIZHINXMIN-NEXT: ret
+ ret half -0.0
+}
diff --git a/llvm/test/CodeGen/RISCV/zfh-imm.ll b/llvm/test/CodeGen/RISCV/zfh-imm.ll
deleted file mode 100644
index 62b97c3294421b..00000000000000
--- a/llvm/test/CodeGen/RISCV/zfh-imm.ll
+++ /dev/null
@@ -1,107 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfh < %s \
-; RUN: | FileCheck --check-prefix=RV32IZFH %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfh,+d < %s \
-; RUN: | FileCheck --check-prefix=RV32IDZFH %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfh < %s \
-; RUN: | FileCheck --check-prefix=RV64IZFH %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfh,+d < %s \
-; RUN: | FileCheck --check-prefix=RV64IDZFH %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx < %s \
-; RUN: | FileCheck --check-prefix=RV32IZHINX %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx,+zdinx < %s \
-; RUN: | FileCheck --check-prefix=RV32IZDINXZHINX %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx < %s \
-; RUN: | FileCheck --check-prefix=RV64IZHINX %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx,+zdinx < %s \
-; RUN: | FileCheck --check-prefix=RV64IZDINXZHINX %s
-
-define half @f16_positive_zero(ptr %pf) nounwind {
-; RV32IZFH-LABEL: f16_positive_zero:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x fa0, zero
-; RV32IZFH-NEXT: ret
-;
-; RV32IDZFH-LABEL: f16_positive_zero:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fmv.h.x fa0, zero
-; RV32IDZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: f16_positive_zero:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x fa0, zero
-; RV64IZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: f16_positive_zero:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fmv.h.x fa0, zero
-; RV64IDZFH-NEXT: ret
-;
-; RV32IZHINX-LABEL: f16_positive_zero:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: li a0, 0
-; RV32IZHINX-NEXT: ret
-;
-; RV32IZDINXZHINX-LABEL: f16_positive_zero:
-; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: li a0, 0
-; RV32IZDINXZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: f16_positive_zero:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: li a0, 0
-; RV64IZHINX-NEXT: ret
-;
-; RV64IZDINXZHINX-LABEL: f16_positive_zero:
-; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: li a0, 0
-; RV64IZDINXZHINX-NEXT: ret
- ret half 0.0
-}
-
-define half @f16_negative_zero(ptr %pf) nounwind {
-; RV32IZFH-LABEL: f16_negative_zero:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: lui a0, 1048568
-; RV32IZFH-NEXT: fmv.h.x fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV32IDZFH-LABEL: f16_negative_zero:
-; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: lui a0, 1048568
-; RV32IDZFH-NEXT: fmv.h.x fa0, a0
-; RV32IDZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: f16_negative_zero:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: lui a0, 1048568
-; RV64IZFH-NEXT: fmv.h.x fa0, a0
-; RV64IZFH-NEXT: ret
-;
-; RV64IDZFH-LABEL: f16_negative_zero:
-; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: lui a0, 1048568
-; RV64IDZFH-NEXT: fmv.h.x fa0, a0
-; RV64IDZFH-NEXT: ret
-;
-; RV32IZHINX-LABEL: f16_negative_zero:
-; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a0, 1048568
-; RV32IZHINX-NEXT: ret
-;
-; RV32IZDINXZHINX-LABEL: f16_negative_zero:
-; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: lui a0, 1048568
-; RV32IZDINXZHINX-NEXT: ret
-;
-; RV64IZHINX-LABEL: f16_negative_zero:
-; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a0, 1048568
-; RV64IZHINX-NEXT: ret
-;
-; RV64IZDINXZHINX-LABEL: f16_negative_zero:
-; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: lui a0, 1048568
-; RV64IZDINXZHINX-NEXT: ret
- ret half -0.0
-}
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