[PATCH] D156855: [X86] Special handle for v1i1 during ExtractBitFromMaskVector

[Phoebe Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4d6f4c9c93c1: [X86] Special handle for v1i1 during ExtractBitFromMaskVector (authored by pengfei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156855/new/

https://reviews.llvm.org/D156855

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr64322.ll


Index: llvm/test/CodeGen/X86/pr64322.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr64322.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s
+
+ at G = global <1 x i1> <i1 true>
+ at G.1 = global i1 false
+
+define void @foo(i32 %x) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq G at GOTPCREL(%rip), %rax
+; CHECK-NEXT:    kmovb (%rax), %k0
+; CHECK-NEXT:    kmovd %k0, %eax
+; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    movq G.1 at GOTPCREL(%rip), %rcx
+; CHECK-NEXT:    movb %al, (%rcx)
+; CHECK-NEXT:    retq
+  %LGV = load <1 x i1>, ptr @G
+  %E = extractelement <1 x i1> %LGV, i32 %x
+  store i1 %E, ptr @G.1
+  ret void
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -17619,6 +17619,19 @@
     unsigned NumElts = VecVT.getVectorNumElements();
     // Extending v8i1/v16i1 to 512-bit get better performance on KNL
     // than extending to 128/256bit.
+    if (NumElts == 1) {
+      if (Subtarget.hasDQI()) {
+        Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
+                          DAG.getUNDEF(MVT::v8i1), Vec,
+                          DAG.getIntPtrConstant(0, dl));
+        return DAG.getBitcast(MVT::i8, Vec);
+      }
+      Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
+                        DAG.getUNDEF(MVT::v16i1), Vec,
+                        DAG.getIntPtrConstant(0, dl));
+      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+                         DAG.getBitcast(MVT::i16, Vec));
+    }
     MVT ExtEltVT = (NumElts <= 8) ? MVT::getIntegerVT(128 / NumElts) : MVT::i8;
     MVT ExtVecVT = MVT::getVectorVT(ExtEltVT, NumElts);
     SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec);


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