[PATCH] D156777: [SelectionDAG] Add/Improve cases in `isKnownNeverZero`

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5091
+      case ISD::SIGN_EXTEND:
+      case ISD::ANY_EXTEND:
+        V = V.getOperand(0);
----------------
Looking through any_extend seems wrong, the high bits may not be 0 as they're undefined


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5100
+
+  Op = PeekThroughCasts(Op);
+
----------------
Should this just go through the recursive case like normal?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5169-5172
+    APInt MaxCnt = computeKnownBits(Op.getOperand(1), Depth + 1).getMaxValue();
+    if (MaxCnt.ule(ValKnown.getBitWidth()) &&
+        !ValKnown.One.lshr(MaxCnt).isZero())
       return true;
----------------
Should try the RHS operand first as it's canonically simpler


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156777/new/

https://reviews.llvm.org/D156777