[llvm] e1aa4e7 - [Statepoint] Use correct RegisterClass for spilling

Danila Malyutin via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 20 06:00:09 PDT 2023


Author: Danila Malyutin
Date: 2023-07-20T16:00:00+03:00
New Revision: e1aa4e7b383e37442df6bb49f4f3db2069487765

URL: https://github.com/llvm/llvm-project/commit/e1aa4e7b383e37442df6bb49f4f3db2069487765
DIFF: https://github.com/llvm/llvm-project/commit/e1aa4e7b383e37442df6bb49f4f3db2069487765.diff

LOG: [Statepoint] Use correct RegisterClass for spilling

Copy propagation might have changed the register class of the register

Differential Revision: https://reviews.llvm.org/D155792

Added: 
    

Modified: 
    llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
    llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 0b32d69afeb286..75504ef32250c5 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -407,7 +407,6 @@ class StatepointState {
   void spillRegisters() {
     for (Register Reg : RegsToSpill) {
       int FI = CacheFI.getFrameIndex(Reg, EHPad);
-      const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
 
       NumSpilledRegisters++;
       RegToSlotIdx[Reg] = FI;
@@ -419,6 +418,7 @@ class StatepointState {
       bool IsKill = true;
       MachineBasicBlock::iterator InsertBefore(MI);
       Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI);
+      const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
 
       LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore);
       TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll b/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
index 5dd7d40030c19f..055944a14b514d 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll
@@ -1,8 +1,27 @@
-; XFAIL: *
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub --version 3
 ; REQUIRES: asserts
-; RUN: llc -verify-machineinstrs -max-registers-for-gc-values=256 -mtriple=aarch64-none-linux-gnu < %s
+; RUN: llc -verify-machineinstrs -max-registers-for-gc-values=256 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
 
+; Verify that FixupStatepointCallerSaved pass uses correct intruction for spilling a register after copyprop
 define dso_local ptr addrspace(1) @foo(ptr addrspace(1) %arg) gc "statepoint-example" personality ptr null {
+; CHECK-LABEL: foo:
+; CHECK:       .Lfunc_begin0:
+; CHECK-NEXT:    .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    sub sp, sp, #48
+; CHECK-NEXT:    stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset w19, -8
+; CHECK-NEXT:    .cfi_offset w30, -16
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    str d0, [sp, #8] // 8-byte Folded Spill
+; CHECK-NEXT:    str q0, [sp, #16]
+; CHECK-NEXT:    bl baz // 8-byte Folded Reload
+; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:    ldp x19, x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-NEXT:    ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT:    add sp, sp, #48
+; CHECK-NEXT:    ret
   %load = load <2 x ptr addrspace(1)>, ptr addrspace(1) %arg, align 8
   %extractelement = extractelement <2 x ptr addrspace(1)> %load, i64 0
   %call = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr nonnull elementtype(void ()) @baz, i32 0, i32 0, i32 0, i32 0) [ "deopt"(ptr addrspace(1) %extractelement), "gc-live"(<2 x ptr addrspace(1)> %load) ]


        


More information about the llvm-commits mailing list