[llvm] 697f605 - [DAG] hoistLogicOpWithSameOpcodeHands - ensure SIGN_EXTEND_INREG nodes have the same extension value type

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-07-20T10:44:46+01:00
New Revision: 697f60598ec303efc0e9b092af1dbea2c46ebc56

URL: https://github.com/llvm/llvm-project/commit/697f60598ec303efc0e9b092af1dbea2c46ebc56
DIFF: https://github.com/llvm/llvm-project/commit/697f60598ec303efc0e9b092af1dbea2c46ebc56.diff

LOG: [DAG] hoistLogicOpWithSameOpcodeHands - ensure SIGN_EXTEND_INREG nodes have the same extension value type

Fix bug in the check for matching SIGN_EXTEND_INREG types

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/X86/scalar-ext-logic.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 45a9a182130161..7673ac5a8eaf3b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5706,7 +5706,7 @@ SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
   SDLoc DL(N);
   if (ISD::isExtOpcode(HandOpcode) || ISD::isExtVecInRegOpcode(HandOpcode) ||
       (HandOpcode == ISD::SIGN_EXTEND_INREG &&
-       N0.getOperand(1) == N0.getOperand(1))) {
+       N0.getOperand(1) == N1.getOperand(1))) {
     // If both operands have other uses, this transform would create extra
     // instructions without eliminating anything.
     if (!N0.hasOneUse() && !N1.hasOneUse())

diff  --git a/llvm/test/CodeGen/X86/scalar-ext-logic.ll b/llvm/test/CodeGen/X86/scalar-ext-logic.ll
index 95e2705e53db77..9926a5be6688c2 100644
--- a/llvm/test/CodeGen/X86/scalar-ext-logic.ll
+++ b/llvm/test/CodeGen/X86/scalar-ext-logic.ll
@@ -35,7 +35,7 @@ define i32 @sextinreg_i32(ptr %p0, ptr %p1) {
   ret i32 %and
 }
 
-; TODO: MISMATCH and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i2)
+; MISMATCH and(sextinreg(v0,i2),sextinreg(v1,i5)) != sextinreg(and(v0,v1),i2)
 define i32 @sextinreg_i32_mismatch(ptr %p0, ptr %p1) {
 ; X86-LABEL: sextinreg_i32_mismatch:
 ; X86:       # %bb.0:
@@ -43,18 +43,22 @@ define i32 @sextinreg_i32_mismatch(ptr %p0, ptr %p1) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movzbl (%ecx), %ecx
 ; X86-NEXT:    movzbl (%eax), %eax
+; X86-NEXT:    shll $30, %ecx
+; X86-NEXT:    sarl $30, %ecx
+; X86-NEXT:    shll $27, %eax
+; X86-NEXT:    sarl $27, %eax
 ; X86-NEXT:    andl %ecx, %eax
-; X86-NEXT:    shll $30, %eax
-; X86-NEXT:    sarl $30, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sextinreg_i32_mismatch:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movzbl (%rdi), %ecx
 ; X64-NEXT:    movzbl (%rsi), %eax
+; X64-NEXT:    shll $30, %ecx
+; X64-NEXT:    sarl $30, %ecx
+; X64-NEXT:    shll $27, %eax
+; X64-NEXT:    sarl $27, %eax
 ; X64-NEXT:    andl %ecx, %eax
-; X64-NEXT:    shll $30, %eax
-; X64-NEXT:    sarl $30, %eax
 ; X64-NEXT:    retq
   %v0 = load i8, ptr %p0, align 1
   %v1 = load i8, ptr %p1, align 1