[llvm] cdee88a - [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-18T09:49:23-07:00
New Revision: cdee88a2e061d529f442a0d01a18ed0688fc207a

URL: https://github.com/llvm/llvm-project/commit/cdee88a2e061d529f442a0d01a18ed0688fc207a
DIFF: https://github.com/llvm/llvm-project/commit/cdee88a2e061d529f442a0d01a18ed0688fc207a.diff

LOG: [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.

This allows TII isCopyInstrImpl to consider them copies.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155140

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/test/CodeGen/RISCV/rvv/copyprop.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 6cf3dbda5b016e..6e5ee8043e9292 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1683,7 +1683,7 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
     RVVConstraint = NoConstraint in {
 // A future extension may relax the vector register alignment restrictions.
 foreach n = [1, 2, 4, 8] in {

diff  --git a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
index 7c9429906ab619..eb4c8bfdd67f9a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
@@ -23,8 +23,7 @@
   ; CHECK-NEXT:    li a2, 128
   ; CHECK-NEXT:    bgeu a0, a2, .LBB0_2
   ; CHECK-NEXT:  .LBB0_4: # %entry
-  ; CHECK-NEXT:    vmv1r.v v8, v9
-  ; CHECK-NEXT:    vse64.v v8, (a1)
+  ; CHECK-NEXT:    vse64.v v9, (a1)
   ; CHECK-NEXT:    ret
   entry:
     ret void