[PATCH] D155476: [RISCV] Split BEXT and BEXTI Write classes. NFC.

[Michael Maitland via Phabricator via llvm-commits]

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BEXT and BEXTI may behave differently from other Zbs instructions.
Split the write classes so these differences may be modeled by
scheduler models.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155476

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVScheduleZb.td


Index: llvm/lib/Target/RISCV/RISCVScheduleZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVScheduleZb.td
+++ llvm/lib/Target/RISCV/RISCVScheduleZb.td
@@ -30,8 +30,10 @@
 def WriteCLMUL       : SchedWrite; // CLMUL/CLMULR/CLMULH
 
 // Zbs extension
-def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV/BEXT
-def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI
+def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV
+def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI
+def WriteBEXT : SchedWrite; // BEXT
+def WriteBEXTI : SchedWrite; // BEXTI
 
 // Zbkb extension
 def WriteBREV8       : SchedWrite; // brev8
@@ -132,6 +134,8 @@
 let Unsupported = true in {
 def : WriteRes<WriteSingleBit, []>;
 def : WriteRes<WriteSingleBitImm, []>;
+def : WriteRes<WriteBEXT, []>;
+def : WriteRes<WriteBEXTI, []>;
 
 def : ReadAdvance<ReadSingleBit, 0>;
 def : ReadAdvance<ReadSingleBitImm, 0>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -351,7 +351,7 @@
            Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
 let IsSignExtendingOpW = 1 in
 def BEXT : ALU_rr<0b0100100, 0b101, "bext">,
-           Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
+           Sched<[WriteBEXT, ReadSingleBit, ReadSingleBit]>;
 
 def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
@@ -361,7 +361,7 @@
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 let IsSignExtendingOpW = 1 in
 def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
-            Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
+            Sched<[WriteBEXTI, ReadSingleBitImm]>;
 } // Predicates = [HasStdExtZbs]
 
 // These instructions were named xperm.n and xperm.b in the last version of


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