[llvm] fda45d9 - [RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 17 08:47:53 PDT 2023
Author: Craig Topper
Date: 2023-07-17T08:47:42-07:00
New Revision: fda45d9198c848a3cfa4c2f9f4a1162cf3a202d4
URL: https://github.com/llvm/llvm-project/commit/fda45d9198c848a3cfa4c2f9f4a1162cf3a202d4
DIFF: https://github.com/llvm/llvm-project/commit/fda45d9198c848a3cfa4c2f9f4a1162cf3a202d4.diff
LOG: [RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC
This is a case that D155288 won't get.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D155327
Added:
Modified:
llvm/test/CodeGen/RISCV/condops.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index e43fa4f9acc690..a36077955b7f27 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
-; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
; RV32I-LABEL: zero1:
@@ -3309,3 +3309,117 @@ bb2: ; preds = %bb2, %bb
bb7: ; preds = %bb2
ret void
}
+
+define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) {
+; RV32I-LABEL: setune_32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: feq.s a2, fa0, fa1
+; RV32I-NEXT: beqz a2, .LBB56_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB56_2:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: setune_32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: feq.s a2, fa0, fa1
+; RV64I-NEXT: beqz a2, .LBB56_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: .LBB56_2:
+; RV64I-NEXT: ret
+;
+; RV64XVENTANACONDOPS-LABEL: setune_32:
+; RV64XVENTANACONDOPS: # %bb.0:
+; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1
+; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT: ret
+;
+; RV64XTHEADCONDMOV-LABEL: setune_32:
+; RV64XTHEADCONDMOV: # %bb.0:
+; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa1
+; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT: ret
+;
+; RV32ZICOND-LABEL: setune_32:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: feq.s a2, fa0, fa1
+; RV32ZICOND-NEXT: xori a2, a2, 1
+; RV32ZICOND-NEXT: czero.nez a1, a1, a2
+; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: setune_32:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: feq.s a2, fa0, fa1
+; RV64ZICOND-NEXT: xori a2, a2, 1
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
+ %rc = fcmp une float %a, %b
+ %sel = select i1 %rc, i32 %rs1, i32 %rs2
+ ret i32 %sel
+}
+
+define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) {
+; RV32I-LABEL: setune_64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: feq.s a4, fa0, fa1
+; RV32I-NEXT: beqz a4, .LBB57_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: .LBB57_2:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: setune_64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: feq.s a2, fa0, fa1
+; RV64I-NEXT: beqz a2, .LBB57_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: .LBB57_2:
+; RV64I-NEXT: ret
+;
+; RV64XVENTANACONDOPS-LABEL: setune_64:
+; RV64XVENTANACONDOPS: # %bb.0:
+; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1
+; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV64XVENTANACONDOPS-NEXT: or a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT: ret
+;
+; RV64XTHEADCONDMOV-LABEL: setune_64:
+; RV64XTHEADCONDMOV: # %bb.0:
+; RV64XTHEADCONDMOV-NEXT: feq.s a2, fa0, fa1
+; RV64XTHEADCONDMOV-NEXT: th.mvnez a0, a1, a2
+; RV64XTHEADCONDMOV-NEXT: ret
+;
+; RV32ZICOND-LABEL: setune_64:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: feq.s a4, fa0, fa1
+; RV32ZICOND-NEXT: xori a4, a4, 1
+; RV32ZICOND-NEXT: czero.nez a2, a2, a4
+; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
+; RV32ZICOND-NEXT: or a0, a0, a2
+; RV32ZICOND-NEXT: czero.nez a2, a3, a4
+; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
+; RV32ZICOND-NEXT: or a1, a1, a2
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: setune_64:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: feq.s a2, fa0, fa1
+; RV64ZICOND-NEXT: xori a2, a2, 1
+; RV64ZICOND-NEXT: czero.nez a1, a1, a2
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
+ %rc = fcmp une float %a, %b
+ %sel = select i1 %rc, i64 %rs1, i64 %rs2
+ ret i64 %sel
+}
More information about the llvm-commits
mailing list