[PATCH] D155142: Add PBNDKB instruction.

Freddy, Ye via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jul 16 18:47:19 PDT 2023


FreddyYe updated this revision to Diff 540843.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155142/new/

https://reviews.llvm.org/D155142

Files:
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Target/X86/X86InstrSystem.td
  llvm/test/MC/Disassembler/X86/pbndkb.txt
  llvm/test/MC/X86/pbndkb.s
  llvm/test/MC/X86/x86_errors.s


Index: llvm/test/MC/X86/x86_errors.s
===================================================================
--- llvm/test/MC/X86/x86_errors.s
+++ llvm/test/MC/X86/x86_errors.s
@@ -187,3 +187,6 @@
 // 32: 12: error: immediate must be an integer in range [0, 15]
 // 64: 12: error: immediate must be an integer in range [0, 15]
 vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2
+
+// 32: error: instruction requires: 64-bit mode
+pbndkb
Index: llvm/test/MC/X86/pbndkb.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/pbndkb.s
@@ -0,0 +1,7 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: pbndkb
+// CHECK: encoding: [0x0f,0x01,0xc7]
+          pbndkb
+
Index: llvm/test/MC/Disassembler/X86/pbndkb.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/pbndkb.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s
+
+# CHECK: pbndkb
+0x0f,0x01,0xc7
+
Index: llvm/lib/Target/X86/X86InstrSystem.td
===================================================================
--- llvm/lib/Target/X86/X86InstrSystem.td
+++ llvm/lib/Target/X86/X86InstrSystem.td
@@ -429,7 +429,8 @@
 def WRMSRNS : I<0x01, MRM_C6, (outs), (ins), "wrmsrns", []>, PS;
 let Defs = [EAX, EDX], Uses = [ECX] in
 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
-
+let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
+def PBNDKB : I<0x01, MRM_C7, (outs), (ins), "pbndkb", []>, PS;
 let Uses = [RSI, RDI, RCX], Predicates = [In64BitMode] in {
 def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, XS;
 def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, XD;
Index: llvm/docs/ReleaseNotes.rst
===================================================================
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -276,6 +276,7 @@
 
 * ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend.
   ``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
+* Add support for the ``PBNDKB`` instruction.
 
 
 Changes to the OCaml bindings


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