[PATCH] D155328: [RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y is 0 or 1.

[Mikhail Gudim via Phabricator via llvm-commits]

mgudim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12728
+    return SDValue();
+
   case RISCVISD::SELECT_CC: {
----------------
Why not express this using pattern?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155328/new/

https://reviews.llvm.org/D155328