[llvm] b8e29db - [RISCV] Common remaining operand logic in performCombineVMergeAndVOps [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-07-13T11:27:16-07:00
New Revision: b8e29dbe54879dd75315fe4471bdcfe250809740

URL: https://github.com/llvm/llvm-project/commit/b8e29dbe54879dd75315fe4471bdcfe250809740
DIFF: https://github.com/llvm/llvm-project/commit/b8e29dbe54879dd75315fe4471bdcfe250809740.diff

LOG: [RISCV] Common remaining operand logic in performCombineVMergeAndVOps [nfc]

We can share the code for both the unmasked and masked cases, and add a missing consistency assert in the process.

This is a subset of Luke's D155063.  I'm splitting pieces and landing them in the process of convincing myself all the individual transforms are in fact correct.  This is the last major piece.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9008531fc68cf1..8c13f95c4015db 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3346,38 +3346,22 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
 
 
   SmallVector<SDValue, 8> Ops;
-  if (IsMasked) {
-    Ops.push_back(False);
-    if (RISCVII::hasRoundModeOp(TrueTSFlags)) {
-      // For masked "VOp" with rounding mode operand, that is interfaces like
-      // (..., vm, rm, vl, policy).
-      // Check the rounding mode pseudo nodes under RISCVInstrInfoVPseudos.td
-      SDValue RoundMode = True->getOperand(TrueVLIndex - 1);
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex - 2);
-      Ops.append({Mask, RoundMode});
-    } else {
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex - 1);
-      Ops.push_back(Mask);
-    }
-  } else {
-    Ops.push_back(False);
-    if (RISCVII::hasRoundModeOp(TrueTSFlags)) {
-      // For unmasked "VOp" with rounding mode operand, that is interfaces like
-      // (..., rm, vl) or (..., rm, vl, policy).
-      // Its masked version is (..., vm, rm, vl, policy).
-      // Check the rounding mode pseudo nodes under RISCVInstrInfoVPseudos.td
-      SDValue RoundMode = True->getOperand(TrueVLIndex - 1);
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex - 1);
-      Ops.append({Mask, RoundMode});
-    } else {
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex);
-      Ops.push_back(Mask);
-    }
-  }
+  Ops.push_back(False);
+
+  const bool HasRoundingMode = RISCVII::hasRoundModeOp(TrueTSFlags);
+  const unsigned NormalOpsEnd = TrueVLIndex - IsMasked - HasRoundingMode;
+  assert(!IsMasked || NormalOpsEnd == Info->MaskOpIdx);
+  Ops.append(True->op_begin() + HasTiedDest, True->op_begin() + NormalOpsEnd);
+
+  Ops.push_back(Mask);
+
+  // For unmasked "VOp" with rounding mode operand, that is interfaces like
+  // (..., rm, vl) or (..., rm, vl, policy).
+  // Its masked version is (..., vm, rm, vl, policy).
+  // Check the rounding mode pseudo nodes under RISCVInstrInfoVPseudos.td
+  if (HasRoundingMode)
+    Ops.push_back(True->getOperand(TrueVLIndex - 1));
+
   Ops.append({VL, SEW, PolicyOp});
 
   // Result node should have chain operand of True.