[PATCH] D154960: [DAG] Use legal shift amount type in DAGTypeLegalizer::JoinIntegers

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll:109
+; SI-NEXT:    v_or_b32_e32 v2, v1, v0
+; SI-NEXT:    v_and_b32_e32 v1, 0xff00, v2
 ; SI-NEXT:    v_or_b32_e32 v0, v0, v1
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There are still some minor regressions like this one, but I'm inclined to waive them. In this case the v_and is redundant because the result is the same as v1. SimplifyDemandedBits would normally optimize this but in this case it gives up because v2 has multiple uses: https://github.com/llvm/llvm-project/blob/49364503f621d807c4ee80050ab7a0cdb2b05a60/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L1116


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https://reviews.llvm.org/D154960