[llvm] 95d6234 - [RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge refactoring [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 11 10:33:08 PDT 2023
Author: Philip Reames
Date: 2023-07-11T10:32:54-07:00
New Revision: 95d62344c0ebd1c150ef368779af6a31213587c7
URL: https://github.com/llvm/llvm-project/commit/95d62344c0ebd1c150ef368779af6a31213587c7
DIFF: https://github.com/llvm/llvm-project/commit/95d62344c0ebd1c150ef368779af6a31213587c7.diff
LOG: [RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge refactoring [nfc]
After D154245 lands, we have greatly simplified the possible configurations for an entry in the RISCVMaskedPseudo table. This change goes through and reworks everything which uses that table to exploit the available simplifications.
To justify the correctness here, let me note that we no longer had any use of HasTU=true. We were left with only the HasTu=false, and IsCombined=true|false cases. The only usage is IsCombined=false was for the comparison operations. At the moment, these operations are the only ones in the table without vector policy operands. Instead of switching on the pseudo value, we can just check the VecPolicy flag instead.
It may be worth adding a passthru operand to the comparisons (which is actually needed to represent tail undefined vs tail agnostic), and a vector policy operand (which is strictly unneeded) just for consistency, but we can do that in a follow up patch for some further simplification if desired.
Note that we do have a few _TU pseudos left at this point. It's simply that none of them are in the RISCVMaskedPseudo table, and thus don't participate in our post-ISEL transforms.
Differential Revision: https://reviews.llvm.org/D154620
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 99a54d3ed44d69..5c1edcf2bd9ea9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -41,22 +41,6 @@ namespace llvm::RISCV {
#include "RISCVGenSearchableTables.inc"
} // namespace llvm::RISCV
-static unsigned getLastNonGlueOrChainOpIdx(const SDNode *Node) {
- assert(Node->getNumOperands() > 0 && "Node with no operands");
- unsigned LastOpIdx = Node->getNumOperands() - 1;
- if (Node->getOperand(LastOpIdx).getValueType() == MVT::Glue)
- --LastOpIdx;
- if (Node->getOperand(LastOpIdx).getValueType() == MVT::Other)
- --LastOpIdx;
- return LastOpIdx;
-}
-
-static unsigned getVecPolicyOpIdx(const SDNode *Node, const MCInstrDesc &MCID) {
- assert(RISCVII::hasVecPolicyOp(MCID.TSFlags));
- (void)MCID;
- return getLastNonGlueOrChainOpIdx(Node);
-}
-
void RISCVDAGToDAGISel::PreprocessISelDAG() {
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
@@ -3167,46 +3151,27 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(SDNode *N) {
if (!usesAllOnesMask(N, MaskOpIdx))
return false;
- // Retrieve the tail policy operand index, if any.
- std::optional<unsigned> TailPolicyOpIdx;
- const MCInstrDesc &MaskedMCID = TII->get(N->getMachineOpcode());
-
- bool UseTUPseudo = false;
- if (RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags)) {
- TailPolicyOpIdx = getVecPolicyOpIdx(N, MaskedMCID);
- // Some operations are their own TU.
- if (I->UnmaskedTUPseudo == I->UnmaskedPseudo) {
- UseTUPseudo = true;
- } else {
- if (!isImplicitDef(N->getOperand(0))) {
- // Keep the true-masked instruction when there is no unmasked TU
- // instruction
- if (I->UnmaskedTUPseudo == I->MaskedPseudo)
- return false;
- UseTUPseudo = true;
- }
- }
- }
- unsigned Opc = UseTUPseudo ? I->UnmaskedTUPseudo : I->UnmaskedPseudo;
+ // There are two classes of pseudos in the table - compares and
+ // everything else. See the comment on RISCVMaskedPseudo for details.
+ const unsigned Opc = I->UnmaskedPseudo;
const MCInstrDesc &MCID = TII->get(Opc);
-
- // If this instruction is tail agnostic, the unmasked instruction should not
- // have a tied destination.
+ const bool UseTUPseudo = RISCVII::hasVecPolicyOp(MCID.TSFlags);
#ifndef NDEBUG
- bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
- assert((UseTUPseudo == HasTiedDest) && "Unexpected pseudo to transform to");
+ const MCInstrDesc &MaskedMCID = TII->get(N->getMachineOpcode());
+ assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ==
+ RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
+ "Masked and unmasked pseudos are inconsistent");
+ const bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
+ assert(UseTUPseudo == HasTiedDest && "Unexpected pseudo structure");
#endif
SmallVector<SDValue, 8> Ops;
// Skip the merge operand at index 0 if !UseTUPseudo.
for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
- // Skip the mask, the policy (if the unmasked doesn't have a policy op), and
- // the Glue.
+ // Skip the mask, and the Glue.
SDValue Op = N->getOperand(I);
- if (I == MaskOpIdx ||
- (I == TailPolicyOpIdx && !RISCVII::hasVecPolicyOp(MCID.TSFlags)) ||
- Op.getValueType() == MVT::Glue)
+ if (I == MaskOpIdx || Op.getValueType() == MVT::Glue)
continue;
Ops.push_back(Op);
}
@@ -3269,17 +3234,10 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
bool IsMasked = false;
const RISCV::RISCVMaskedPseudoInfo *Info =
- RISCV::lookupMaskedIntrinsicByUnmaskedTA(TrueOpc);
+ RISCV::lookupMaskedIntrinsicByUnmasked(TrueOpc);
if (!Info && HasTiedDest) {
- Info = RISCV::lookupMaskedIntrinsicByUnmaskedTU(TrueOpc);
- if (Info && !isImplicitDef(True->getOperand(0)))
- // We only support the TA form of the _TU pseudos
- return false;
- // FIXME: Expect undef operand here?
- if (!Info) {
- Info = RISCV::getMaskedPseudoInfo(TrueOpc);
- IsMasked = true;
- }
+ Info = RISCV::getMaskedPseudoInfo(TrueOpc);
+ IsMasked = true;
}
if (!Info)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index b4377a8073eb28..70452bf09b5451 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -254,7 +254,6 @@ struct VLX_VSXPseudo {
struct RISCVMaskedPseudoInfo {
uint16_t MaskedPseudo;
uint16_t UnmaskedPseudo;
- uint16_t UnmaskedTUPseudo;
uint8_t MaskOpIdx;
};
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index d6a8c4d09bc1d8..e1c2b65b121245 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -528,30 +528,20 @@ def RISCVVIntrinsicsTable : GenericTable {
}
// Describes the relation of a masked pseudo to the unmasked variants.
-// (HasTU = true, IsCombined = false)
-// Has both a TA (unsuffixed) and _TU variant defined. TU variant
-// may (or may not) have a vector policy operand.
-// (HasTU = false, IsCombined = false)
-// No TA (unsuffixed) or _TU variants. Masked version is only pseudo
-// (HasTU = false, IsCombined = true)
-// The unsuffixed version has a merge operand; no explicit _TU variant
-// exists. The unsuffixed version has a policy operand, and can thus
-// represent all policy states.
-// (HasTU = true, IsCombined = true)
-// Invalid and unused state.
-class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true, bit IsCombined = false> {
+// Note that all masked variants (in this table) have exactly one
+// unmasked variant. For all but compares, both the masked and
+// unmasked variant have a passthru and policy operand. For compares,
+// neither has a policy op, and only the masked version has a passthru.
+class RISCVMaskedPseudo<bits<4> MaskIdx> {
Pseudo MaskedPseudo = !cast<Pseudo>(NAME);
Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME));
- Pseudo UnmaskedTUPseudo = !cond(HasTU : !cast<Pseudo>(!subst("_MASK", "", NAME # "_TU")),
- IsCombined : UnmaskedPseudo,
- true : MaskedPseudo);
bits<4> MaskOpIdx = MaskIdx;
}
def RISCVMaskedPseudosTable : GenericTable {
let FilterClass = "RISCVMaskedPseudo";
let CppTypeName = "RISCVMaskedPseudoInfo";
- let Fields = ["MaskedPseudo", "UnmaskedPseudo", "UnmaskedTUPseudo", "MaskOpIdx"];
+ let Fields = ["MaskedPseudo", "UnmaskedPseudo", "MaskOpIdx"];
let PrimaryKey = ["MaskedPseudo"];
let PrimaryKeyName = "getMaskedPseudoInfo";
}
@@ -565,16 +555,11 @@ class RISCVVLE<bit M, bit Str, bit F, bits<3> S, bits<3> L> {
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
-def lookupMaskedIntrinsicByUnmaskedTA : SearchIndex {
+def lookupMaskedIntrinsicByUnmasked : SearchIndex {
let Table = RISCVMaskedPseudosTable;
let Key = ["UnmaskedPseudo"];
}
-def lookupMaskedIntrinsicByUnmaskedTU : SearchIndex {
- let Table = RISCVMaskedPseudosTable;
- let Key = ["UnmaskedTUPseudo"];
-}
-
def RISCVVLETable : GenericTable {
let FilterClass = "RISCVVLE";
let CppTypeName = "VLEPseudo";
@@ -1600,8 +1585,7 @@ multiclass VPseudoUSLoad {
VLESched<LInfo>;
def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoUSLoadMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU=*/false,
- /*IsCombined=*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
VLESched<LInfo>;
}
}
@@ -1619,8 +1603,7 @@ multiclass VPseudoFFLoad {
VLFSched<LInfo>;
def "E" # eew # "FF_V_" # LInfo # "_MASK":
VPseudoUSLoadFFMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU=*/false,
- /*IsCombined=*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
VLFSched<LInfo>;
}
}
@@ -1648,8 +1631,7 @@ multiclass VPseudoSLoad {
VLSSched<eew, LInfo>;
def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoSLoadMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU=*/false,
- /*IsCombined=*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
VLSSched<eew, LInfo>;
}
}
@@ -1678,8 +1660,7 @@ multiclass VPseudoILoad<bit Ordered> {
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU=*/false,
- /*IsCombined=*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
}
}
@@ -1811,9 +1792,7 @@ multiclass VPseudoVID_V {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 1,
- /*HasTU=*/false,
- /*IsCombined=*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
}
}
@@ -1842,9 +1821,7 @@ multiclass VPseudoVIOT_M {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
}
}
@@ -1878,8 +1855,7 @@ multiclass VPseudoBinary<VReg RetClass,
Constraint>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false,
- /*IsCombined*/ true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -1897,9 +1873,7 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
Op1Class,
Op2Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3,
- /*HasTU*/false,
- /*IsCombined*/true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -1914,7 +1888,7 @@ multiclass VPseudoBinaryM<VReg RetClass,
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -1931,9 +1905,7 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
Constraint>;
def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3,
- /*HasTU*/ false,
- /*IsCombined*/ true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -2240,9 +2212,7 @@ multiclass VPseudoVCLS_V {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
}
}
@@ -2263,9 +2233,7 @@ multiclass VPseudoVSQR_V {
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
}
@@ -2282,9 +2250,7 @@ multiclass VPseudoVRCP_V {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
}
}
@@ -2302,7 +2268,7 @@ multiclass PseudoVEXT_VF2 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -2320,7 +2286,7 @@ multiclass PseudoVEXT_VF4 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -2338,7 +2304,7 @@ multiclass PseudoVEXT_VF8 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -3090,7 +3056,7 @@ multiclass VPseudoTernaryWithPolicy<VReg RetClass,
let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false, /*IsCombined*/true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -3136,7 +3102,7 @@ multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false, /*IsTernary*/ true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
@@ -3424,9 +3390,7 @@ multiclass VPseudoConversion<VReg RetClass,
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
}
}
@@ -3439,9 +3403,7 @@ multiclass VPseudoConversionRM<VReg RetClass,
Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2,
- /*HasTU*/ false,
- /*IsCombined*/true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
}
}
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