[PATCH] D154837: [RISCV] Simplify the definitions of interrupt CSRs

[Wang Pengcheng via Phabricator via llvm-commits]

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For `CSR_Interrupt`, we can generate the register list via a single
`sequence`.

For `CSR_XLEN_F32_Interrupt` and `CSR_XLEN_F64_Interrupt`, I don't
see the reason why we need to keep the order the same as how we used
to allocate registers (and we have changed the order in D146488 <https://reviews.llvm.org/D146488>), so
I fold them into one `sequence`.

There are some *.ll changes because of the order change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154837

Files:
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
  llvm/test/CodeGen/RISCV/interrupt-attr.ll

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