[PATCH] D154739: [RISCV] Check for alignment when selecting whole register loads/stores

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:69
   // Store
-  def : Pat<(store type:$rs2, GPR:$rs1),
+  def : Pat<(whole_reg_store type:$rs2, GPR:$rs1),
             (store_instr reg_class:$rs2, GPR:$rs1)>;
----------------
luke wrote:
> I'm actually not sure if we need to do this for stores anymore. From the spec:
> 
> > The load instructions have an EEW encoded in the mew and width