[PATCH] D154536: [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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As noted by @reames, we should be checking that the memory access is aligned to
the element size (or the unaligned vector memory access feature is enabled)
before lowering vlseg/vsseg intrinsics via the interleaved access pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154536

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

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