[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P

[QIHAN CAI via Phabricator via llvm-commits]

realqhc updated this revision to Diff 537200.
realqhc added a comment.

rename RVInst to CVInst, add core-v to instruction description, use RVInstR to simplify CVInstALU_rr and CVInstAlu_r


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153748/new/

https://reviews.llvm.org/D153748

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/MC/RISCV/corev/XCValu-invalid.s
  llvm/test/MC/RISCV/corev/XCValu-valid.s

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