[PATCH] D142348: [RISCV][Docs] Document code generation for vector extension

Sat Jul 1 22:56:23 PDT 2023

barannikov88 added a comment.

It would be great if there was a section describing how vector registers are spilled / restored.
Or, more generally, how the stack space is allocated for registers that don't have length know at compile time.

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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:20
+Vector registers are partitioned (i.e. densely packed) in elements whose size in bits is a power of two, ranging from 8 to a maximum called ``ELEN``.
+``ELEN`` is also a power of two and :math:`\texttt{ELEN} \leq \texttt{VLEN}`.
+
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"is also a power of two" repeats the previous sentence.

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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:35
+
+- When :math:`\text{LMUL} = 1` the vector instructions operate on the (32) vector registers.
+- When :math:`\text{LMUL} \lt 1` the vector instructions operate on the lowest half, quarter or eighth of a vector register.
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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:40-42
+  - :math:`\text{LMUL}=2` has 16 groups: ``v0``, ``v2``, ``v4``, ..., ``v28``, ``v30``
+  - :math:`\text{LMUL}=4` has 8 groups: ``v0``, ``v4``, ``v8``, ``v12``, ``v16``, ``v20``, ``v24``, ``v28``
+  - :math:`\text{LMUL}=8` has 4 groups: ``v0``, ``v8``, ``v16``, ``v24``
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Should the group names be the same as in "Register classes" seciton, v0m4 etc.?

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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:128
+  - ``e32,m8``: Group the registers together into groups of 8 (:math:`\text{LMUL}=8`) and partition them into 32-bit elements.
+  - ``ta,mu``: Be tail agnostic and mask agnostic: We don't care about what's in the elements that aren't processed.
+  - ``a0``: Try and process ``a0`` elements, or as many as the hardware supports.
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