[llvm] b7e8a55 - [AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 30 08:35:51 PDT 2023
Author: Ivan Kosarev
Date: 2023-06-30T16:35:46+01:00
New Revision: b7e8a55a83bf6a69a0fb6630a584cf48f8ae69a9
URL: https://github.com/llvm/llvm-project/commit/b7e8a55a83bf6a69a0fb6630a584cf48f8ae69a9
DIFF: https://github.com/llvm/llvm-project/commit/b7e8a55a83bf6a69a0fb6630a584cf48f8ae69a9.diff
LOG: [AMDGPU][AsmParser][NFC] Simplify parsing of sopp_brtarget operands.
Also refine the definitions while there.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: mbrkusanin
Differential Revision: https://reviews.llvm.org/D154061
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 483a6e9b3c5314..e324922ff31886 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -858,9 +858,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return Kind == Expression;
}
- bool isSoppBrTarget() const {
- return isExpr() || isImm();
- }
+ bool isSOPPBrTarget() const { return isExpr() || isImm(); }
bool isSWaitCnt() const;
bool isDepCtr() const;
@@ -971,8 +969,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
if (isRegKind())
addRegOperands(Inst, N);
- else if (isExpr())
- Inst.addOperand(MCOperand::createExpr(Expr));
else
addImmOperands(Inst, N);
}
@@ -1014,15 +1010,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
addRegWithInputModsOperands(Inst, N);
}
- void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
- if (isImm())
- addImmOperands(Inst, N);
- else {
- assert(isExpr());
- Inst.addOperand(MCOperand::createExpr(Expr));
- }
- }
-
static void printImmTy(raw_ostream& OS, ImmTy Type) {
switch (Type) {
case ImmTyNone: OS << "None"; break;
@@ -1726,7 +1713,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseSendMsg(OperandVector &Operands);
OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
- OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
+ OperandMatchResultTy parseSOPPBrTarget(OperandVector &Operands);
OperandMatchResultTy parseBoolReg(OperandVector &Operands);
bool parseSwizzleOperand(int64_t &Op,
@@ -2084,6 +2071,11 @@ uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
}
void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
+ if (isExpr()) {
+ Inst.addOperand(MCOperand::createExpr(Expr));
+ return;
+ }
+
if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
Inst.getNumOperands())) {
addLiteralImmOperand(Inst, Imm.Val,
@@ -7674,7 +7666,7 @@ bool AMDGPUOperand::isGPRIdxMode() const {
//===----------------------------------------------------------------------===//
OperandMatchResultTy
-AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
+AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
// Make sure we are not parsing something
// that looks like a label or an expression but is not.
@@ -9052,8 +9044,8 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;
case MCK_SSrcF32:
return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
- case MCK_SoppBrTarget:
- return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
+ case MCK_SOPPBrTarget:
+ return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;
case MCK_VReg32OrOff:
return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
case MCK_InterpSlot:
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index fcc2863af0644a..b974031f958caa 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -74,7 +74,7 @@ static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
return OpIdx;
}
-static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
uint64_t Addr,
const MCDisassembler *Decoder) {
auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 97819eb31abdc5..6296ff387ff4fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -921,16 +921,11 @@ def set_glc : SDNodeXForm<timm, [{
// Custom Operands
//===----------------------------------------------------------------------===//
-def SoppBrTarget : AsmOperandClass {
- let Name = "SoppBrTarget";
- let ParserMethod = "parseSOppBrTarget";
-}
-
-def sopp_brtarget : Operand<OtherVT> {
+def SOPPBrTarget : CustomOperand<OtherVT> {
+ let PrintMethod = "printOperand";
let EncoderMethod = "getSOPPBrEncoding";
- let DecoderMethod = "decodeSoppBrTarget";
+ let DecoderMethod = "decodeSOPPBrTarget";
let OperandType = "OPERAND_PCREL";
- let ParserMatchClass = SoppBrTarget;
}
def si_ga : Operand<iPTR>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index c733e04d1d7f92..1a2115439427f6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -500,7 +500,7 @@ def SI_ILLEGAL_COPY : SPseudoInstSI <
// Branch on undef scc. Used to avoid intermediate copy from
// IMPLICIT_DEF to SCC.
-def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> {
+def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins SOPPBrTarget:$simm16)> {
let isTerminator = 1;
let usesCustomInserter = 1;
let isBranch = 1;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index b6d370c977b238..bee996d1b0df14 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -784,7 +784,7 @@ class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
class SOPK_32_BR <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
opName,
(outs),
- (ins sopp_brtarget:$simm16, SReg_32:$sdst),
+ (ins SOPPBrTarget:$simm16, SReg_32:$sdst),
"$sdst, $simm16",
pattern> {
let Defs = [EXEC];
@@ -864,7 +864,7 @@ let isCommutable = 1, DisableEncoding = "$src0",
let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
def S_CBRANCH_I_FORK : SOPK_Pseudo <
"s_cbranch_i_fork",
- (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16),
+ (outs), (ins SReg_64:$sdst, SOPPBrTarget:$simm16),
"$sdst, $simm16"
>;
@@ -942,7 +942,7 @@ let SubtargetPredicate = isGFX9Plus in {
def S_CALL_B64 : SOPK_Pseudo<
"s_call_b64",
(outs SReg_64:$sdst),
- (ins sopp_brtarget:$simm16),
+ (ins SOPPBrTarget:$simm16),
"$sdst, $simm16"> {
let isCall = 1;
}
@@ -1195,60 +1195,60 @@ let SubtargetPredicate = isGFX10Plus in {
let isBranch = 1, SchedRW = [WriteBranch] in {
let isBarrier = 1 in {
defm S_BRANCH : SOPP_With_Relaxation<
- "s_branch" , (ins sopp_brtarget:$simm16), "$simm16",
+ "s_branch" , (ins SOPPBrTarget:$simm16), "$simm16",
[(br bb:$simm16)]>;
}
let Uses = [SCC] in {
defm S_CBRANCH_SCC0 : SOPP_With_Relaxation<
- "s_cbranch_scc0" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_scc0" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_SCC1 : SOPP_With_Relaxation <
- "s_cbranch_scc1" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_scc1" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
} // End Uses = [SCC]
let Uses = [VCC] in {
defm S_CBRANCH_VCCZ : SOPP_With_Relaxation <
- "s_cbranch_vccz" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_vccz" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation <
- "s_cbranch_vccnz" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_vccnz" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
} // End Uses = [VCC]
let Uses = [EXEC] in {
defm S_CBRANCH_EXECZ : SOPP_With_Relaxation <
- "s_cbranch_execz" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_execz" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation <
- "s_cbranch_execnz" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_execnz" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
} // End Uses = [EXEC]
defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation <
- "s_cbranch_cdbgsys" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation <
- "s_cbranch_cdbgsys_and_user" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys_and_user" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation <
- "s_cbranch_cdbgsys_or_user" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys_or_user" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation <
- "s_cbranch_cdbguser" , (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbguser" , (ins SOPPBrTarget:$simm16),
"$simm16"
>;
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