[llvm] 02f94a6 - [RISCV] Bump vector crypto to v1.0.0-rc1
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 28 19:53:23 PDT 2023
Author: 4vtomat
Date: 2023-06-28T19:53:07-07:00
New Revision: 02f94a655fb6ee494df6cd9e136e7ab713be2043
URL: https://github.com/llvm/llvm-project/commit/02f94a655fb6ee494df6cd9e136e7ab713be2043
DIFF: https://github.com/llvm/llvm-project/commit/02f94a655fb6ee494df6cd9e136e7ab713be2043.diff
LOG: [RISCV] Bump vector crypto to v1.0.0-rc1
Differential Revision: https://reviews.llvm.org/D153836
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 7f0016f14c8da4..70a1ff97bac886 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -553,124 +553,124 @@
// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvbb0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvbb1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvbb0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvbb1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
-// CHECK-ZVBB-EXT: __riscv_zvbb 9000{{$}}
+// CHECK-ZVBB-EXT: __riscv_zvbb 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvbc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvbc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvbc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvbc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
-// CHECK-ZVBC-EXT: __riscv_zvbc 9000{{$}}
+// CHECK-ZVBC-EXT: __riscv_zvbc 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkg0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkg1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkg0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkg1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
-// CHECK-ZVKG-EXT: __riscv_zvkg 9000{{$}}
+// CHECK-ZVKG-EXT: __riscv_zvkg 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkn0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvkn1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkn0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvkn1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
-// CHECK-ZVKN-EXT: __riscv_zvkn 9000{{$}}
+// CHECK-ZVKN-EXT: __riscv_zvkn 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvknc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvknc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvknc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvknc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
-// CHECK-ZVKNC-EXT: __riscv_zvknc 9000{{$}}
+// CHECK-ZVKNC-EXT: __riscv_zvknc 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkng0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvkng1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkng0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvkng1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
-// CHECK-ZVKNG-EXT: __riscv_zvkng 9000{{$}}
+// CHECK-ZVKNG-EXT: __riscv_zvkng 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvknha0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvknha1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvknha0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvknha1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
-// CHECK-ZVKNHA-EXT: __riscv_zvknha 9000{{$}}
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvknhb0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvknhb1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvknhb0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvknhb1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
-// CHECK-ZVKNHB-EXT: __riscv_zvknhb 9000{{$}}
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkned0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkned1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkned0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkned1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
-// CHECK-ZVKNED-EXT: __riscv_zvkned 9000{{$}}
+// CHECK-ZVKNED-EXT: __riscv_zvkned 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvks0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvks1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvks0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvks1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
-// CHECK-ZVKS-EXT: __riscv_zvks 9000{{$}}
+// CHECK-ZVKS-EXT: __riscv_zvks 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvksc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvksc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvksc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvksc1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
-// CHECK-ZVKSC-EXT: __riscv_zvksc 9000{{$}}
+// CHECK-ZVKSC-EXT: __riscv_zvksc 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksed0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksed1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksed0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksed1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
-// CHECK-ZVKSED-EXT: __riscv_zvksed 9000{{$}}
+// CHECK-ZVKSED-EXT: __riscv_zvksed 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvksg0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvksg1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvksg0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvksg1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
-// CHECK-ZVKSG-EXT: __riscv_zvksg 9000{{$}}
+// CHECK-ZVKSG-EXT: __riscv_zvksg 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksh0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksh1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksh0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksh1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
-// CHECK-ZVKSH-EXT: __riscv_zvksh 9000{{$}}
+// CHECK-ZVKSH-EXT: __riscv_zvksh 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkt0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkt0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
-// CHECK-ZVKT-EXT: __riscv_zvkt 9000{{$}}
+// CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c416999bfe3fa1..2f1942d75058ac 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -210,7 +210,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`__.
``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
- LLVM implements the `0.9.7 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230531/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+ LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 7b12abcdc801ed..3e218a59d17e2c 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -162,27 +162,27 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"ztso", RISCVExtensionVersion{0, 1}},
- {"zvbb", RISCVExtensionVersion{0, 9}},
- {"zvbc", RISCVExtensionVersion{0, 9}},
+ {"zvbb", RISCVExtensionVersion{1, 0}},
+ {"zvbc", RISCVExtensionVersion{1, 0}},
{"zvfbfmin", RISCVExtensionVersion{0, 6}},
{"zvfbfwma", RISCVExtensionVersion{0, 6}},
{"zvfh", RISCVExtensionVersion{0, 1}},
// vector crypto
- {"zvkg", RISCVExtensionVersion{0, 9}},
- {"zvkn", RISCVExtensionVersion{0, 9}},
- {"zvknc", RISCVExtensionVersion{0, 9}},
- {"zvkned", RISCVExtensionVersion{0, 9}},
- {"zvkng", RISCVExtensionVersion{0, 9}},
- {"zvknha", RISCVExtensionVersion{0, 9}},
- {"zvknhb", RISCVExtensionVersion{0, 9}},
- {"zvks", RISCVExtensionVersion{0, 9}},
- {"zvksc", RISCVExtensionVersion{0, 9}},
- {"zvksed", RISCVExtensionVersion{0, 9}},
- {"zvksg", RISCVExtensionVersion{0, 9}},
- {"zvksh", RISCVExtensionVersion{0, 9}},
- {"zvkt", RISCVExtensionVersion{0, 9}},
+ {"zvkg", RISCVExtensionVersion{1, 0}},
+ {"zvkn", RISCVExtensionVersion{1, 0}},
+ {"zvknc", RISCVExtensionVersion{1, 0}},
+ {"zvkned", RISCVExtensionVersion{1, 0}},
+ {"zvkng", RISCVExtensionVersion{1, 0}},
+ {"zvknha", RISCVExtensionVersion{1, 0}},
+ {"zvknhb", RISCVExtensionVersion{1, 0}},
+ {"zvks", RISCVExtensionVersion{1, 0}},
+ {"zvksc", RISCVExtensionVersion{1, 0}},
+ {"zvksed", RISCVExtensionVersion{1, 0}},
+ {"zvksg", RISCVExtensionVersion{1, 0}},
+ {"zvksh", RISCVExtensionVersion{1, 0}},
+ {"zvkt", RISCVExtensionVersion{1, 0}},
};
static void verifyTables() {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 3ab2d81000f9a7..85985e80d6c51b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions from the standard 'Zvk',
-// Vector Cryptography Instructions extension, version 0.9.7.
+// Vector Cryptography Instructions extension, version 1.0.0-rc1.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 5911e2748d5e7a..fad90b30ab3e49 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -228,21 +228,21 @@
; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
-; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
-; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
-; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
-; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
-; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
-; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
+; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
+; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
+; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
+; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
@@ -314,21 +314,21 @@
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
-; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
-; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
-; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
-; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
-; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
-; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
-; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
-; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
+; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
+; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
+; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
+; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 3bda1d2a2d1582..aee5c7cdc651a8 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -111,50 +111,50 @@
.attribute arch, "rv32izbc1p0"
# CHECK: attribute 5, "rv32i2p1_zbc1p0"
-.attribute arch, "rv32i_zve64x_zvbb0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbb1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvbc0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbc1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvkg0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkg1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
-.attribute arch, "rv32i_zve64x_zvkn0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkn1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvknc0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknc1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvkng0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkng1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvknha0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvknha1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
-.attribute arch, "rv32i_zve64x_zvknhb0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknhb1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvkned0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkned1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
-.attribute arch, "rv32i_zve64x_zvks0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvks1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvksc0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksc1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvksg0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksg1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvksed0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvksed1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
-.attribute arch, "rv32i_zve32x_zvksh0p9"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvksh1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
-.attribute arch, "rv32i_zvkt0p9"
-# CHECK: attribute 5, "rv32i2p1_zvkt0p9"
+.attribute arch, "rv32i_zvkt1p0"
+# CHECK: attribute 5, "rv32i2p1_zvkt1p0"
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
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