[llvm] d39b4ce - [test] Replace aarch64-*-eabi with aarch64
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 20:02:58 PDT 2023
Author: Fangrui Song
Date: 2023-06-27T20:02:52-07:00
New Revision: d39b4ce3ce8a3c256e01bdec2b140777a332a633
URL: https://github.com/llvm/llvm-project/commit/d39b4ce3ce8a3c256e01bdec2b140777a332a633
DIFF: https://github.com/llvm/llvm-project/commit/d39b4ce3ce8a3c256e01bdec2b140777a332a633.diff
LOG: [test] Replace aarch64-*-eabi with aarch64
Using "eabi" for aarch64 targets is a common mistake and warned by Clang Driver.
We want to avoid it elsewhere as well. Just use the common "aarch64" without
other triple components.
Added:
Modified:
clang/test/CodeGen/aarch64-args-hfa.c
clang/test/CodeGen/aarch64-mops.c
llvm/test/Analysis/CostModel/AArch64/abs.ll
llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
llvm/test/Analysis/CostModel/AArch64/arith-usat.ll
llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
llvm/test/CodeGen/AArch64/abd-combine.ll
llvm/test/CodeGen/AArch64/arm64-trn.ll
llvm/test/CodeGen/AArch64/bcax.ll
llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
llvm/test/CodeGen/AArch64/cmp-const-max.ll
llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll
llvm/test/CodeGen/AArch64/combine-andintoload.ll
llvm/test/CodeGen/AArch64/eor3.ll
llvm/test/CodeGen/AArch64/f16-imm.ll
llvm/test/CodeGen/AArch64/fcopysign.ll
llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
llvm/test/CodeGen/AArch64/fp-intrinsics.ll
llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll
llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll
llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
llvm/test/CodeGen/AArch64/fpimm.ll
llvm/test/CodeGen/AArch64/hadd-combine.ll
llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
llvm/test/CodeGen/AArch64/inline-asm-clobber.ll
llvm/test/CodeGen/AArch64/inlineasm-X-allocation.ll
llvm/test/CodeGen/AArch64/ld1postmul.ll
llvm/test/CodeGen/AArch64/ldradr.ll
llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
llvm/test/CodeGen/AArch64/load-insert-zero.ll
llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
llvm/test/CodeGen/AArch64/mulcmle.ll
llvm/test/CodeGen/AArch64/neon-extadd.ll
llvm/test/CodeGen/AArch64/neon-rshrn.ll
llvm/test/CodeGen/AArch64/rax1.ll
llvm/test/CodeGen/AArch64/reassocmls.ll
llvm/test/CodeGen/AArch64/shift-accumulate.ll
llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
llvm/test/CodeGen/AArch64/sign-return-address.ll
llvm/test/CodeGen/AArch64/special-reg.ll
llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
llvm/test/CodeGen/AArch64/stack-tagging-musttail.ll
llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll
llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
llvm/test/CodeGen/AArch64/strict-fp-opt.ll
llvm/test/CodeGen/AArch64/strpre-str-merge.mir
llvm/test/CodeGen/AArch64/sve-pr62151.ll
llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
llvm/test/CodeGen/AArch64/sve2-eor3.ll
llvm/test/CodeGen/AArch64/tbl-loops.ll
llvm/test/CodeGen/AArch64/tiny_supported.ll
llvm/test/CodeGen/AArch64/typepromotion-cost.ll
llvm/test/CodeGen/AArch64/vacg.ll
llvm/test/CodeGen/AArch64/vector-fcvt.ll
llvm/test/CodeGen/AArch64/vldn_shuffle.ll
llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll
llvm/test/MC/AArch64/align.s
llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll
llvm/test/Transforms/InstCombine/AArch64/demandelts.ll
llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
llvm/test/Transforms/SLPVectorizer/AArch64/fpsat.ll
llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
Removed:
################################################################################
diff --git a/clang/test/CodeGen/aarch64-args-hfa.c b/clang/test/CodeGen/aarch64-args-hfa.c
index 400375f8cb789..fbfedc7db7913 100644
--- a/clang/test/CodeGen/aarch64-args-hfa.c
+++ b/clang/test/CodeGen/aarch64-args-hfa.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS
+// RUN: %clang_cc1 -triple aarch64 -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS
// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-abi darwinpcs -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DARWIN
// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - -x c %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS
diff --git a/clang/test/CodeGen/aarch64-mops.c b/clang/test/CodeGen/aarch64-mops.c
index c0f151837c751..36e1e0af6640c 100644
--- a/clang/test/CodeGen/aarch64-mops.c
+++ b/clang/test/CodeGen/aarch64-mops.c
@@ -1,7 +1,7 @@
-// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion -target-feature +mops -target-feature +mte -w -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-MOPS %s
-// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion -target-feature +mops -Wno-implicit-function-declaration -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
-// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion -Wno-implicit-function-declaration -target-feature +mte -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
-// RUN: not %clang_cc1 -triple aarch64-arm-unknown-eabi -Wno-int-conversion -Wno-implicit-function-declaration -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: %clang_cc1 -triple aarch64 -Wno-int-conversion -target-feature +mops -target-feature +mte -w -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-MOPS %s
+// RUN: not %clang_cc1 -triple aarch64 -Wno-int-conversion -target-feature +mops -Wno-implicit-function-declaration -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: not %clang_cc1 -triple aarch64 -Wno-int-conversion -Wno-implicit-function-declaration -target-feature +mte -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
+// RUN: not %clang_cc1 -triple aarch64 -Wno-int-conversion -Wno-implicit-function-declaration -w -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NOMOPS %s
#include <arm_acle.h>
#include <stddef.h>
diff --git a/llvm/test/Analysis/CostModel/AArch64/abs.ll b/llvm/test/Analysis/CostModel/AArch64/abs.ll
index e8e03c9e03146..6406cf1124d48 100644
--- a/llvm/test/Analysis/CostModel/AArch64/abs.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/abs.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64 < %s | FileCheck %s --check-prefix=RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64 < %s | FileCheck %s --check-prefix=SIZE
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll b/llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
index e7f7e4db3923e..2267d9b88c970 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64 < %s | FileCheck %s --check-prefix=RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64 < %s | FileCheck %s --check-prefix=SIZE
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-usat.ll b/llvm/test/Analysis/CostModel/AArch64/arith-usat.ll
index a2252d08a6ca4..5a131f23847b1 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-usat.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-usat.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=RECIP
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64-none-eabi < %s | FileCheck %s --check-prefix=SIZE
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64 < %s | FileCheck %s --check-prefix=RECIP
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-size -mtriple=aarch64 < %s | FileCheck %s --check-prefix=SIZE
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
index d16a1a0f3346e..38b9558f426f2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s
define dso_local void @fn() {
; CHECK-LABEL: fn:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
index e14c43a7923e1..4995024a7229d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny -run-pass=instruction-select -verify-machineinstrs -O0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -code-model=tiny -run-pass=instruction-select -verify-machineinstrs -O0 %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll
index e6891f2d53cbd..bb0e9ae503ed4 100644
--- a/llvm/test/CodeGen/AArch64/abd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <8 x i16> @abdu_base(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: abdu_base:
diff --git a/llvm/test/CodeGen/AArch64/arm64-trn.ll b/llvm/test/CodeGen/AArch64/arm64-trn.ll
index b728a39cf00de..9dd78a3c3668e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-trn.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-trn.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s --check-prefixes=CHECKLE
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECKLE
; RUN: llc < %s -mtriple=aarch64_be-none-eabi | FileCheck %s --check-prefixes=CHECKBE
define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind {
diff --git a/llvm/test/CodeGen/AArch64/bcax.ll b/llvm/test/CodeGen/AArch64/bcax.ll
index 15e8b3421bf9b..e3c73c36e534b 100644
--- a/llvm/test/CodeGen/AArch64/bcax.ll
+++ b/llvm/test/CodeGen/AArch64/bcax.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
define <2 x i64> @bcax_64x2(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
; SHA3-LABEL: bcax_64x2:
diff --git a/llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll b/llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
index 58b2e1ba46846..1c216e7357215 100644
--- a/llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+bf16 | FileCheck %s
define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v4i16:
diff --git a/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
index 9712420be9f67..222d7435ff742 100644
--- a/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+bf16 | FileCheck %s
; bfloat16x4_t test_vcreate_bf16(uint64_t a) { return vcreate_bf16(a); }
define <4 x bfloat> @test_vcreate_bf16(i64 %a) nounwind {
diff --git a/llvm/test/CodeGen/AArch64/cmp-const-max.ll b/llvm/test/CodeGen/AArch64/cmp-const-max.ll
index 0d5846f067930..2f1919a4f9394 100644
--- a/llvm/test/CodeGen/AArch64/cmp-const-max.ll
+++ b/llvm/test/CodeGen/AArch64/cmp-const-max.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
+; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64 -fast-isel=false | FileCheck %s
define i32 @ule_64_max(i64 %p) {
diff --git a/llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll b/llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll
index 9a2f4840f79e2..ee8303f52d51c 100644
--- a/llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll
+++ b/llvm/test/CodeGen/AArch64/code-model-tiny-abs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -code-model=tiny < %s | FileCheck %s
@var8 = dso_local global i8 0
@var16 = dso_local global i16 0
diff --git a/llvm/test/CodeGen/AArch64/combine-andintoload.ll b/llvm/test/CodeGen/AArch64/combine-andintoload.ll
index 82e6ae936253f..3e7e23f573c6a 100644
--- a/llvm/test/CodeGen/AArch64/combine-andintoload.ll
+++ b/llvm/test/CodeGen/AArch64/combine-andintoload.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -o - | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -o - | FileCheck %s
; RUN: llc < %s -mtriple=aarch64_be-none-eabi -o - | FileCheck %s --check-prefix=CHECKBE
define i64 @load32_and16_and(ptr %p, i64 %y) {
diff --git a/llvm/test/CodeGen/AArch64/eor3.ll b/llvm/test/CodeGen/AArch64/eor3.ll
index 539db2b6fec78..06ae6b09d002e 100644
--- a/llvm/test/CodeGen/AArch64/eor3.ll
+++ b/llvm/test/CodeGen/AArch64/eor3.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
define <16 x i8> @eor3_16x8_left(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
; SHA3-LABEL: eor3_16x8_left:
diff --git a/llvm/test/CodeGen/AArch64/f16-imm.ll b/llvm/test/CodeGen/AArch64/f16-imm.ll
index 6fa994bb1d42d..58793bf19f3a6 100644
--- a/llvm/test/CodeGen/AArch64/f16-imm.ll
+++ b/llvm/test/CodeGen/AArch64/f16-imm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+no-zcz-fp | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-NOZCZ
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-ZCZ
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFP16
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16,+no-zcz-fp | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-NOZCZ
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16,+zcz | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-ZCZ
+; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFP16
define half @Const0() {
; CHECK-NOZCZ-LABEL: Const0:
diff --git a/llvm/test/CodeGen/AArch64/fcopysign.ll b/llvm/test/CodeGen/AArch64/fcopysign.ll
index 6d5389389db5c..53188b01d34a1 100644
--- a/llvm/test/CodeGen/AArch64/fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/fcopysign.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-neon | FileCheck -check-prefix=CHECK-NONEON %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=-neon | FileCheck -check-prefix=CHECK-NONEON %s
; Check that selection dag legalization of fcopysign works in cases with
;
diff erent modes for the arguments.
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
index 0a9fa6c849bbf..48062c9a54b5d 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
+; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
+; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; Check that constrained fp intrinsics are correctly lowered.
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
index b78798531e01f..d5a99f2d77089 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi %s -disable-strictnode-mutation -o - | FileCheck %s
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -disable-strictnode-mutation -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - | FileCheck %s
; Check that constrained fp vector intrinsics are correctly lowered.
diff --git a/llvm/test/CodeGen/AArch64/fp-intrinsics.ll b/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
index 29aeb204bf7e8..f80a8df18a03a 100644
--- a/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/fp-intrinsics.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
; Check that constrained fp intrinsics are correctly lowered.
diff --git a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
index 74552735179c3..6aef8cd9ba619 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
index 99e173d289d5e..ae94a9d004f15 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16 --check-prefix=CHECK-COMMON
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16 --check-prefix=CHECK-COMMON
define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index d46d31e297490..949def3ff634e 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
; CHECK-CVT-LABEL: add_h:
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll b/llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
index f1a28907d1639..0fe34704d0135 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v4i16:
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll b/llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll
index f0edfde6cf567..291ace4859614 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
; Simple load of v4i16
define <4 x half> @load_64(ptr nocapture readonly %a) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll b/llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll
index abded8183d340..ef947dc6c05bd 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
define void @nvcast_v2i32(ptr %a) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
index 63bb3b9099f50..97c3a4937cda7 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
; float16x4_t select_64(float16x4_t a, float16x4_t b, uint16x4_t c) { return vbsl_u16(c, a, b); }
define <4 x half> @select_64(<4 x half> %a, <4 x half> %b, <4 x i16> %c) #0 {
diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll
index 58d79d3e5998e..85ef19d38043f 100644
--- a/llvm/test/CodeGen/AArch64/fpimm.ll
+++ b/llvm/test/CodeGen/AArch64/fpimm.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LARGE
-; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -code-model=tiny -verify-machineinstrs < %s | FileCheck %s
@varf32 = global float 0.0
@varf64 = global double 0.0
diff --git a/llvm/test/CodeGen/AArch64/hadd-combine.ll b/llvm/test/CodeGen/AArch64/hadd-combine.ll
index 73e3a9f1d5697..2269d75cdbb9e 100644
--- a/llvm/test/CodeGen/AArch64/hadd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/hadd-combine.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <8 x i16> @haddu_base(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: haddu_base:
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll b/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
index ad743ae434c51..35b2d587f41aa 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
@@ -1,7 +1,7 @@
; Check that not only do we warn about clobbering x19 we also say
; what it is used for.
-; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+; RUN: llc <%s -mtriple=aarch64 2>&1 | FileCheck %s
; CHECK: warning: inline asm clobber list contains reserved registers: X19
; CHECK-NEXT: note: Reserved registers on the clobber list
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-clobber.ll b/llvm/test/CodeGen/AArch64/inline-asm-clobber.ll
index 028cf0b6db125..666b7774757ae 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-clobber.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-clobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+; RUN: llc <%s -mtriple=aarch64 2>&1 | FileCheck %s
; CHECK: warning: inline asm clobber list contains reserved registers: SP
diff --git a/llvm/test/CodeGen/AArch64/inlineasm-X-allocation.ll b/llvm/test/CodeGen/AArch64/inlineasm-X-allocation.ll
index 1d7a24e3e6e7c..d6393e80c270a 100644
--- a/llvm/test/CodeGen/AArch64/inlineasm-X-allocation.ll
+++ b/llvm/test/CodeGen/AArch64/inlineasm-X-allocation.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=-fp-armv8 %s -o - | FileCheck %s -check-prefix=nofp
+; RUN: llc -mtriple=aarch64 -mattr=-fp-armv8 %s -o - | FileCheck %s -check-prefix=nofp
; In the novfp case, the compiler is forced to assign a core register,
; even if the input is a float.
diff --git a/llvm/test/CodeGen/AArch64/ld1postmul.ll b/llvm/test/CodeGen/AArch64/ld1postmul.ll
index 44f6ee093c5ce..1553aab9046ed 100644
--- a/llvm/test/CodeGen/AArch64/ld1postmul.ll
+++ b/llvm/test/CodeGen/AArch64/ld1postmul.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc -mtriple=aarch64 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
+; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
define ptr @mul_v16i8(ptr %p, ptr %ps, <16 x i8> %t) {
; CHECK-LABEL: mul_v16i8:
diff --git a/llvm/test/CodeGen/AArch64/ldradr.ll b/llvm/test/CodeGen/AArch64/ldradr.ll
index 2e6ca86e3227e..e5f3fd3d770ba 100644
--- a/llvm/test/CodeGen/AArch64/ldradr.ll
+++ b/llvm/test/CodeGen/AArch64/ldradr.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -code-model=tiny -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -code-model=tiny -verify-machineinstrs | FileCheck %s
%struct.T = type <{ i32, i64, i8, i32 }>
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index 5e7886356c17a..5662975150b30 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64 -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
---
name: 1-ldrwpre-ldrwui-merge
diff --git a/llvm/test/CodeGen/AArch64/load-insert-zero.ll b/llvm/test/CodeGen/AArch64/load-insert-zero.ll
index bc21d8b5201a2..692e9edfedad4 100644
--- a/llvm/test/CodeGen/AArch64/load-insert-zero.ll
+++ b/llvm/test/CodeGen/AArch64/load-insert-zero.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+bf16,+sve | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16,+bf16,+sve | FileCheck %s
define <8 x i8> @loadv8i8(ptr %p) {
; CHECK-LABEL: loadv8i8:
diff --git a/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll b/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
index 8bce4c553755e..18bb4710e31c3 100644
--- a/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
+++ b/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <4 x i16> @mlai16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
; CHECK-LABEL: mlai16_trunc:
diff --git a/llvm/test/CodeGen/AArch64/mulcmle.ll b/llvm/test/CodeGen/AArch64/mulcmle.ll
index 8a359dfc232f2..7a0c946410164 100644
--- a/llvm/test/CodeGen/AArch64/mulcmle.ll
+++ b/llvm/test/CodeGen/AArch64/mulcmle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
define <1 x i64> @v1i64(<1 x i64> %a) {
; CHECK-LABEL: v1i64:
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd.ll b/llvm/test/CodeGen/AArch64/neon-extadd.ll
index 5aa006fd68a59..20c6069f7d188 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple aarch64-none-eabi -o - | FileCheck %s
+; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s
define <8 x i16> @extadds_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
; CHECK-LABEL: extadds_v8i8_i16:
diff --git a/llvm/test/CodeGen/AArch64/neon-rshrn.ll b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
index b29d1a52fb762..563509c75d12d 100644
--- a/llvm/test/CodeGen/AArch64/neon-rshrn.ll
+++ b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple aarch64-none-eabi -o - | FileCheck %s
+; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s
define <16 x i8> @rshrn_v16i16_1(<16 x i16> %a) {
; CHECK-LABEL: rshrn_v16i16_1:
diff --git a/llvm/test/CodeGen/AArch64/rax1.ll b/llvm/test/CodeGen/AArch64/rax1.ll
index 414fa07170ce4..bc1a216df70f0 100644
--- a/llvm/test/CodeGen/AArch64/rax1.ll
+++ b/llvm/test/CodeGen/AArch64/rax1.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64 -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) {
; SHA3-LABEL: rax1:
diff --git a/llvm/test/CodeGen/AArch64/reassocmls.ll b/llvm/test/CodeGen/AArch64/reassocmls.ll
index 62230d16ad6dd..381caffba92eb 100644
--- a/llvm/test/CodeGen/AArch64/reassocmls.ll
+++ b/llvm/test/CodeGen/AArch64/reassocmls.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+sve2 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s
define i64 @smlsl_i64(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; CHECK-LABEL: smlsl_i64:
diff --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index bea01fc6c28e4..2ca6c73d3b831 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <4 x i16> @usra_v4i16(<8 x i8> %0) {
; CHECK-LABEL: usra_v4i16:
diff --git a/llvm/test/CodeGen/AArch64/shuffle-tbl34.ll b/llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
index 28b1f386c998d..30e5bdb8371fb 100644
--- a/llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
+++ b/llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; CHECK: .LCPI0_0:
; CHECK: .byte 0 // 0x0
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
index 903b27dcd793f..3214f4ae7ae44 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck --check-prefixes CHECK,CHECK-V8A %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=v8.3a < %s | FileCheck --check-prefixes CHECK,CHECK-V83A %s
-; RUN: llc -mtriple=aarch64-none-eabi -filetype=obj -o - <%s | llvm-dwarfdump -v - | FileCheck --check-prefix=CHECK-DUMP %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck --check-prefixes CHECK,CHECK-V8A %s
+; RUN: llc -mtriple=aarch64 -mattr=v8.3a < %s | FileCheck --check-prefixes CHECK,CHECK-V83A %s
+; RUN: llc -mtriple=aarch64 -filetype=obj -o - <%s | llvm-dwarfdump -v - | FileCheck --check-prefix=CHECK-DUMP %s
@.str = private unnamed_addr constant [15 x i8] c"some exception\00", align 1
@_ZTIPKc = external dso_local constant ptr
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address.ll b/llvm/test/CodeGen/AArch64/sign-return-address.ll
index 163f172830418..e50ea8097a27e 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=v8.3a < %s | FileCheck --check-prefix CHECK-V83A %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=v8.3a < %s | FileCheck --check-prefix CHECK-V83A %s
; CHECK-LABEL: @leaf
; CHECK-NOT: paci{{[a,b]}}sp
diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
index 4b8c75b70985d..7c02d0b2e1de3 100644
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ b/llvm/test/CodeGen/AArch64/special-reg.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mcpu=cortex-a57 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
define i64 @read_encoded_register() nounwind {
entry:
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll b/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
index 32f01b704350f..66ac04e52394a 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
@@ -1,7 +1,7 @@
; RUN: opt -S -aarch64-stack-tagging %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-unknown-eabi"
+target triple = "aarch64"
define void @f() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
start:
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-musttail.ll b/llvm/test/CodeGen/AArch64/stack-tagging-musttail.ll
index 8d3be9ad07265..430e10cfa01d0 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-musttail.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-musttail.ll
@@ -4,7 +4,7 @@
; RUN: opt -S -aarch64-stack-tagging -stack-tagging-use-stack-safety=0 %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-unknown-eabi"
+target triple = "aarch64"
define dso_local noundef i32 @_Z3bari(i32 noundef %0) sanitize_memtag {
%2 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll b/llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll
index 5f3d6ed88dcd5..e2c41cad29452 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll
@@ -1,7 +1,7 @@
; RUN: opt -S -aarch64-stack-tagging -stack-tagging-use-stack-safety=0 %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-unknown-eabi"
+target triple = "aarch64"
declare void @use8(ptr)
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll b/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
index 75d4419c45e72..06f8cd5241ebf 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
@@ -1,6 +1,6 @@
;; RUN: opt -S -aarch64-stack-tagging %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-unknown-eabi"
+target triple = "aarch64"
define void @f() local_unnamed_addr #0 {
S0:
diff --git a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
index f1e624a4838d4..ec8b4cbb92d5d 100644
--- a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
+++ b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -o - %s | FileCheck %s
; Check that stp are not suppressed at minsize.
diff --git a/llvm/test/CodeGen/AArch64/strict-fp-opt.ll b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
index 17afdf739a2a6..f370e8f05761c 100644
--- a/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
+++ b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
; Div whose result is unused should be removed unless we have strict exceptions
diff --git a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
index 5cee20a66527f..722de6bb343e2 100644
--- a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
+++ b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64 -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
---
name: 1-strwpre-strwui-merge
diff --git a/llvm/test/CodeGen/AArch64/sve-pr62151.ll b/llvm/test/CodeGen/AArch64/sve-pr62151.ll
index 07089dd102118..5ed34f14a0b14 100644
--- a/llvm/test/CodeGen/AArch64/sve-pr62151.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pr62151.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
define i32 @build_interpolation(<2 x i32> %0, <2 x i32> %1, <2 x i32> %2) {
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
index f7cc43c3c2b31..a8b28c756f20b 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+neon,+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+neon,+sve2 -verify-machineinstrs %s -o - | FileCheck %s
define <vscale x 4 x i32> @add_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
; CHECK-LABEL: add_v4i32:
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
index 861f540a7bb53..df2c7fbcb5069 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
; CHECK-LABEL: add_nxv2i64_x:
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
index 38e4b57855ea4..3b1b616a59154 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
; CHECK-LABEL: add_nxv2i64_x:
diff --git a/llvm/test/CodeGen/AArch64/sve2-eor3.ll b/llvm/test/CodeGen/AArch64/sve2-eor3.ll
index 665008ccf7e49..786e8435c0dd5 100644
--- a/llvm/test/CodeGen/AArch64/sve2-eor3.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-eor3.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s
define <vscale x 16 x i8> @eor3_nxv16i8_left(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
; SVE-LABEL: eor3_nxv16i8_left:
diff --git a/llvm/test/CodeGen/AArch64/tbl-loops.ll b/llvm/test/CodeGen/AArch64/tbl-loops.ll
index 8f313df9b36ec..a01a3826e340d 100644
--- a/llvm/test/CodeGen/AArch64/tbl-loops.ll
+++ b/llvm/test/CodeGen/AArch64/tbl-loops.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture noundef readonly %data, i32 noundef %width) {
; CHECK-LABEL: loop1:
diff --git a/llvm/test/CodeGen/AArch64/tiny_supported.ll b/llvm/test/CodeGen/AArch64/tiny_supported.ll
index 400fde0aa0a9d..035fed97ca247 100644
--- a/llvm/test/CodeGen/AArch64/tiny_supported.ll
+++ b/llvm/test/CodeGen/AArch64/tiny_supported.ll
@@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s
-; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64 -code-model=tiny < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
diff --git a/llvm/test/CodeGen/AArch64/typepromotion-cost.ll b/llvm/test/CodeGen/AArch64/typepromotion-cost.ll
index c1b3057bfbfd9..3aed4cb671c02 100644
--- a/llvm/test/CodeGen/AArch64/typepromotion-cost.ll
+++ b/llvm/test/CodeGen/AArch64/typepromotion-cost.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -o - %s -mtriple=aarch64-none-eabi | FileCheck %s --check-prefix=CHECK-O2
-; RUN: llc -o - %s -mtriple=aarch64-none-eabi -O3 | FileCheck %s --check-prefix=CHECK-O3
+; RUN: llc -o - %s -mtriple=aarch64 | FileCheck %s --check-prefix=CHECK-O2
+; RUN: llc -o - %s -mtriple=aarch64 -O3 | FileCheck %s --check-prefix=CHECK-O3
%struct.S = type { i32, i16 }
define i32 @needless_promotion(ptr nocapture noundef readonly %S, i64 noundef %red_cost) {
diff --git a/llvm/test/CodeGen/AArch64/vacg.ll b/llvm/test/CodeGen/AArch64/vacg.ll
index c3556e09b0c94..8f4b34231c8e6 100644
--- a/llvm/test/CodeGen/AArch64/vacg.ll
+++ b/llvm/test/CodeGen/AArch64/vacg.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s
define <4 x i32> @gt_v4f32(<4 x float> %a, <4 x float> %b) {
diff --git a/llvm/test/CodeGen/AArch64/vector-fcvt.ll b/llvm/test/CodeGen/AArch64/vector-fcvt.ll
index 72fe72906a76e..ec6fbc9277428 100644
--- a/llvm/test/CodeGen/AArch64/vector-fcvt.ll
+++ b/llvm/test/CodeGen/AArch64/vector-fcvt.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK
; Note: halves are tested in fp16-v8-instructions.ll.
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index e2357ee2d226d..48d9ecff68d24 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define void @vld2(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
; CHECK-LABEL: vld2:
diff --git a/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
index 201292378221c..e00a64df84bea 100644
--- a/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
+++ b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
define i64 @vscale_lshr(i64 %TC) {
; CHECK-LABEL: vscale_lshr:
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll b/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll
index 7b30f10703e16..5183b62c730b0 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll
@@ -4,7 +4,7 @@
; RUN: opt -S -passes=hwasan -hwasan-use-stack-safety=0 %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-unknown-eabi"
+target triple = "aarch64"
define dso_local noundef i32 @_Z3bari(i32 noundef %0) sanitize_hwaddress {
%2 = alloca i32, align 4
diff --git a/llvm/test/MC/AArch64/align.s b/llvm/test/MC/AArch64/align.s
index e1841c05ce791..73da08673b42f 100644
--- a/llvm/test/MC/AArch64/align.s
+++ b/llvm/test/MC/AArch64/align.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -filetype=obj -triple aarch64-none-eabi %s | llvm-objdump -d - | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple aarch64 %s | llvm-objdump -d - | FileCheck %s
// RUN: llvm-mc -filetype=obj -triple aarch64_be-none-eabi %s | llvm-objdump -d - | FileCheck %s
// CHECK: 0: d2800000 mov x0, #0
diff --git a/llvm/test/MC/AsmParser/AArch64/directive-parse-err.s b/llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
index 754b7afe7aeea..02cdfd7829198 100644
--- a/llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
+++ b/llvm/test/MC/AsmParser/AArch64/directive-parse-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -triple aarch64-none-eabi %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-eabi %s 2>&1 | grep "error:" | count 60
+// RUN: not llvm-mc -triple aarch64 %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 %s 2>&1 | grep "error:" | count 60
// CHECK: [[#@LINE+1]]:19: error: expected newline
.equ ident1, 0 $
diff --git a/llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll b/llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll
index a7eeb3b75da0b..5fea6f669ead6 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=aggressive-instcombine -mtriple aarch64-none-eabi -S | FileCheck %s --check-prefixes=CHECK,CHECK-FP
-; RUN: opt < %s -passes=aggressive-instcombine -mtriple aarch64-none-eabi -mattr=+fullfp16 -S | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: opt < %s -passes=aggressive-instcombine -mtriple aarch64 -S | FileCheck %s --check-prefixes=CHECK,CHECK-FP
+; RUN: opt < %s -passes=aggressive-instcombine -mtriple aarch64 -mattr=+fullfp16 -S | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
define i64 @f32_i32(float %in) {
; CHECK-LABEL: @f32_i32(
diff --git a/llvm/test/Transforms/InstCombine/AArch64/demandelts.ll b/llvm/test/Transforms/InstCombine/AArch64/demandelts.ll
index 394f48ae6b60b..39e0956db22a1 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/demandelts.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/demandelts.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=instcombine -mtriple aarch64-none-eabi < %s | FileCheck %s
+; RUN: opt -S -passes=instcombine -mtriple aarch64 < %s | FileCheck %s
define <2 x float> @fcvtxn(<2 x double> %d1) {
; CHECK-LABEL: @fcvtxn(
diff --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
index eb235ca82c9a7..df698fbafe4e6 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -lsr-preferred-addressing-mode=preindexed %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 -lsr-preferred-addressing-mode=preindexed %s -o - | FileCheck %s
; In LSR for constant offsets and steps, we can generate pre-inc
; accesses by having the offset equal the step and generate a reuse
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/fpsat.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/fpsat.ll
index 72f4f95e1ad36..acdf32dcca48d 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/fpsat.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/fpsat.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=slp-vectorizer -mtriple=aarch64-none-eabi < %s | FileCheck %s
+; RUN: opt -S -passes=slp-vectorizer -mtriple=aarch64 < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll b/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
index 25a002106a9c0..8a3382a75090d 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='vector-combine' -S %s | FileCheck %s
-target triple = "aarch64-none-eabi"
+target triple = "aarch64"
define <16 x i32> @test1(<16 x i32> %x, <16 x i32> %y) {
; CHECK-LABEL: @test1(
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll b/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
index bdd9ef6b3e68f..d69cb75664a8c 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='vector-combine' -S %s | FileCheck %s
-target triple = "aarch64-none-eabi"
+target triple = "aarch64"
define i32 @reducebase_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @reducebase_v4i32(
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
index f111c4101ab00..07113df465ade 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mca -mtriple=aarch64-none-eabi -mcpu=cortex-a57 -iterations=1 -timeline < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a57 -iterations=1 -timeline < %s | FileCheck %s
# CHECK: [0] Code Region
# CHECK: Instructions: 2
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