[lld] ebbfdca - [test] Replace aarch64-arm-none-eabi with aarch64
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 19:36:31 PDT 2023
Author: Fangrui Song
Date: 2023-06-27T19:36:27-07:00
New Revision: ebbfdca586d5543c13617b15d0cdf5b7fdc4fd4a
URL: https://github.com/llvm/llvm-project/commit/ebbfdca586d5543c13617b15d0cdf5b7fdc4fd4a
DIFF: https://github.com/llvm/llvm-project/commit/ebbfdca586d5543c13617b15d0cdf5b7fdc4fd4a.diff
LOG: [test] Replace aarch64-arm-none-eabi with aarch64
Similar to 02e9441d6ca73314afa1973a234dce1e390da1da, but for llvm/test and one
lld/test/ELF test.
Added:
Modified:
lld/test/ELF/eh-frame-cfi-b-key.s
llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
llvm/test/CodeGen/AArch64/a55-fuse-address.mir
llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll
llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
llvm/test/CodeGen/AArch64/aarch64-mops.ll
llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll
llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
llvm/test/CodeGen/AArch64/elim-dead-mi.mir
llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll
llvm/test/CodeGen/AArch64/fptosi-strictfp.ll
llvm/test/CodeGen/AArch64/global-merge-minsize.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll
llvm/test/CodeGen/AArch64/machine_cse_illegal_hoist.ll
llvm/test/CodeGen/AArch64/pr40091.ll
llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
llvm/test/CodeGen/AArch64/tailcall-bitcast-memcpy.ll
llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
llvm/test/DebugInfo/AArch64/return-address-signing.ll
llvm/test/MC/AArch64/armv9a-rme.s
llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt
llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
llvm/test/MC/ELF/cfi-b-key-frame.s
llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
llvm/test/Transforms/SLPVectorizer/AArch64/multiple_reduction.ll
llvm/test/Transforms/SLPVectorizer/AArch64/phi-use-order-scalable.ll
Removed:
################################################################################
diff --git a/lld/test/ELF/eh-frame-cfi-b-key.s b/lld/test/ELF/eh-frame-cfi-b-key.s
index 406674e8b5c8d..fffa23512d316 100644
--- a/lld/test/ELF/eh-frame-cfi-b-key.s
+++ b/lld/test/ELF/eh-frame-cfi-b-key.s
@@ -1,5 +1,5 @@
// REQUIRES: aarch64
-// RUN: llvm-mc -filetype=obj -triple aarch64-arm-none-eabi %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple aarch64 %s -o %t.o
// RUN: ld.lld %t.o -o %t --icf=all --eh-frame-hdr
.globl _start
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
index 35549c5685066..dd7db6eec8ef5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
@@ -4,7 +4,7 @@
# PR36345
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
+ target triple = "aarch64"
; Function Attrs: noinline nounwind optnone
define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {
diff --git a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
index bd6518ae8f0a6..d4e66ec99afff 100644
--- a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
+++ b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
@@ -2,7 +2,7 @@
# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
+ target triple = "aarch64"
@a = dso_local global i32 2, align 4
@b = dso_local global i32 4, align 4
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll b/llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
index df35a4f382504..52b542790e82d 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple aarch64-arm-none-eabi -mattr=+bf16 %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64 -mattr=+bf16 %s -o - | FileCheck %s
define <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-LABEL: test_vbfdot_f32:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll b/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll
index 903da96c3b960..b2643dc8f9dcb 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-arm-none-eabi -asm-verbose=1 -mattr=+bf16 %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64 -asm-verbose=1 -mattr=+bf16 %s -o - | FileCheck %s
%struct.bfloat16x4x2_t = type { [2 x <4 x bfloat>] }
%struct.bfloat16x8x2_t = type { [2 x <8 x bfloat>] }
diff --git a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
index 6db7f2f2534f8..7878bac06472b 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
@@ -3,7 +3,7 @@
# CHECK: add sp, sp, #16
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
+ target triple = "aarch64"
define hidden i32 @foo(i32 %0) {
%2 = alloca [4 x i32], align 4
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
index cea255b225212..de6bbb351e61c 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops | FileCheck %s --check-prefix=CHECK-MOPS
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops | FileCheck %s --check-prefix=CHECK-MOPS
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
index ad1f4a27d5763..bccb70ccd5c03 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte | FileCheck %s --check-prefix=GISel-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte | FileCheck %s --check-prefix=GISel
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops,+mte | FileCheck %s --check-prefix=SDAG
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte | FileCheck %s --check-prefix=GISel-O0
+; RUN: llc %s -o - -mtriple=aarch64 -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte | FileCheck %s --check-prefix=GISel
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops,+mte | FileCheck %s --check-prefix=SDAG
declare ptr @llvm.aarch64.mops.memset.tag(ptr, i8, i64)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index 532a41280ce71..52610ceca481d 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O3
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -global-isel=1 -global-isel-abort=1 -mattr=+mops | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O3
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 | FileCheck %s --check-prefix=SDAG-WITHOUT-MOPS-O2
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops | FileCheck %s --check-prefix=SDAG-MOPS-O2
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O0
+; RUN: llc %s -o - -mtriple=aarch64 -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O3
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O0
+; RUN: llc %s -o - -mtriple=aarch64 -global-isel=1 -global-isel-abort=1 -mattr=+mops | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O3
+; RUN: llc %s -o - -mtriple=aarch64 -O2 | FileCheck %s --check-prefix=SDAG-WITHOUT-MOPS-O2
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops | FileCheck %s --check-prefix=SDAG-MOPS-O2
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
diff --git a/llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll b/llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll
index f95c2957f8637..9d4e79d38d5d1 100644
--- a/llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-arm-none-eabi -mattr=+neon -mattr=+bf16 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64 -mattr=+neon -mattr=+bf16 | FileCheck %s
declare bfloat @llvm.aarch64.neon.bfcvt(float)
declare <8 x bfloat> @llvm.aarch64.neon.bfcvtn(<4 x float>)
diff --git a/llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll b/llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
index 46290beae594d..3b5a2941c8b75 100644
--- a/llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
+++ b/llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
@@ -4,7 +4,7 @@
; FALLBACK: remark: <unknown>:0:0: unable to translate instruction: call: ' tail call void %p()' (in function: bti_enabled)
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; When BTI is enabled, all indirect tail-calls must use x16 or x17 (the intra
; procedure call scratch registers) to hold the address, as these instructions
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
index 1c5f713b0e330..04cce6c7dd6ce 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; a * b + c
define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
index 76e90e92433b3..a0c19f4589f51 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; a * b + c
define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
index 0576475c8168a..3e3c26b74956d 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; a * b + c
define <vscale x 4 x double> @mull_add(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
index b2a4c5c3ef3ad..37fb425b972cf 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to not transform
define <vscale x 4 x half> @complex_add_v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
index 407a2bb347a16..90c0d9e164717 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to not transform
define <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
index 70f2c5a582b6c..5bcb51bca85ec 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <vscale x 4 x half> @complex_mul_v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
index 069817508a5b6..72e5b0eef9d02 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to not transform
define <2 x half> @complex_mul_v2f16(<2 x half> %a, <2 x half> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
index 205df040362f5..ae7be554a0c5e 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <vscale x 4 x float> @complex_add_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
index fce50b6c8ce4f..f8d559eec34be 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
index b3fdfe28f47e9..917f3e5981543 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <vscale x 4 x float> @complex_mul_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
index 5cda0e3b39d9d..b25ea19ae9217 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <2 x float> @complex_mul_v2f32(<2 x float> %a, <2 x float> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
index 42d805f23c63b..4dcc7d48ac01c 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <vscale x 2 x double> @complex_add_v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll
index 54c0fd98f4f4d..1a701b2c53da4 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
index b3a0baf081245..00dbce3591983 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <vscale x 2 x double> @complex_mul_v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
index b72d386be7d83..4de56ee730688 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <2 x double> @complex_mul_v2f64(<2 x double> %a, <2 x double> %b) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
index c6cc42d6a45d3..fdeb4a0f5548f 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <4 x float> @mul_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
index 4d6dad1945bde..3243a691493ca 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
; *p = (a * b);
; return (a * b) * a;
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
index cfa3f3943b1bb..2a034d7037409 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
%"class.std::complex" = type { { double, double } }
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
index 4336dacac492c..a11f67bdcb046 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
%"class.std::complex" = type { { double, double } }
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
index 675b1b8948d11..de6611bed9c3e 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
%"struct.std::complex" = type { { double, double } }
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
index 3a1d909b9d8c7..94f104a44ce26 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Expected to transform
define <4 x float> @simple_mul(<4 x float> %a, <4 x float> %b) {
diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
index b9086f4f5646f..25e8c109c3995 100644
--- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
+++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
@@ -19,7 +19,7 @@
; CHECK-NEXT: stack:
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
+ target triple = "aarch64"
%struct.S = type { i32, i32 }
diff --git a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir
index c7518c9324742..0510a8798a49d 100644
--- a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir
+++ b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
+# RUN: llc -mtriple=aarch64 -o - %s \
# RUN: -run-pass dead-mi-elimination | FileCheck %s
--- |
@c = internal unnamed_addr global [3 x i8] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll b/llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll
index d0f3c82433923..1d213945966a6 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-arm-none-eabi -O1 -opt-bisect-limit=2 -o - %s 2> /dev/null | FileCheck %s
+; RUN: llc -mtriple=aarch64 -O1 -opt-bisect-limit=2 -o - %s 2> /dev/null | FileCheck %s
define dso_local i32 @a() #0 !dbg !7 {
entry:
diff --git a/llvm/test/CodeGen/AArch64/fptosi-strictfp.ll b/llvm/test/CodeGen/AArch64/fptosi-strictfp.ll
index 62c5d4fcc9b1c..cd27a79971e61 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-strictfp.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-strictfp.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
define i128 @test_fixtfti(fp128 %ld) #0 {
; CHECK-LABEL: test_fixtfti:
diff --git a/llvm/test/CodeGen/AArch64/global-merge-minsize.ll b/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
index d54b1b7fd5d8b..8f569ecd9e634 100644
--- a/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
+++ b/llvm/test/CodeGen/AArch64/global-merge-minsize.ll
@@ -1,7 +1,7 @@
; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
@global0 = dso_local local_unnamed_addr global i32 0, align 4
@global1 = dso_local local_unnamed_addr global i32 0, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
index 1c3b0441e6bde..e9492d2a87e15 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
; Function a's outlining candidate contains a sp modifying add without a
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-
diff -scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-
diff -scope-same-key.ll
index 07d561abc1b5e..a5757a70843a9 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-
diff -scope-same-key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-
diff -scope-same-key.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
define void @a() "sign-return-address"="all" {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
index 3e85142ae32ab..0d948f379af1a 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
index cab5dd31a1fde..949afc93ef47f 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -run-pass=prologepilog \
+# RUN: llc -mtriple=aarch64 -run-pass=prologepilog \
# RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
# Check that we save LR to a callee-saved register when possible.
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-
diff -key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-
diff -key.ll
index a127895597355..1e4d6286cd22c 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-
diff -key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-
diff -key.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
define void @a() "sign-return-address"="all" {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
index dbbd924a7147e..82a65cf06f602 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
define void @a() "sign-return-address"="all" "sign-return-address-key"="a_key" nounwind {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
index 81724006a1720..690b803034343 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" nounwind {
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
index 95c71ba4bbd57..33ee4d9decd74 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-arm-none-eabi -enable-machine-outliner \
+; RUN: llc -mtriple aarch64 -enable-machine-outliner \
; RUN: -verify-machineinstrs %s -o - | FileCheck %s
@v = common dso_local global ptr null, align 8
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
index bc4b074a057d0..7bef53b686ad7 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple aarch64-arm-linux-gnu --enable-machine-outliner \
; RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefixes CHECK,V8A %s
-; RUN-V83A: llc -mtriple aarch64-arm-none-eabi -enable-machine-outliner \
+; RUN-V83A: llc -mtriple aarch64 -enable-machine-outliner \
; RUN-V83A: -verify-machineinstrs -mattr=+v8.3a %s -o - > %t
; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-throw.ll b/llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
index 7e4c26e6491cc..3b7285ef8ff42 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi -stop-after=machine-outliner < %s | FileCheck %s -check-prefix=TARGET_FEATURES
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64 -stop-after=machine-outliner < %s | FileCheck %s -check-prefix=TARGET_FEATURES
; Make sure that we haven't added nouwind.
; TARGET_FEATURES: define internal void @OUTLINED_FUNCTION_0()
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll b/llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll
index 2348c22929d15..a0792b0f30973 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi -frame-pointer=non-leaf < %s | FileCheck %s --check-prefix=NOOMIT
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi -frame-pointer=none < %s | FileCheck %s --check-prefix=OMITFP
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64 -frame-pointer=non-leaf < %s | FileCheck %s --check-prefix=NOOMIT
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64 -frame-pointer=none < %s | FileCheck %s --check-prefix=OMITFP
define void @_Z1giii(i32 %x, i32 %y, i32 %z) minsize {
; NOOMIT-LABEL: _Z1giii:
diff --git a/llvm/test/CodeGen/AArch64/machine_cse_illegal_hoist.ll b/llvm/test/CodeGen/AArch64/machine_cse_illegal_hoist.ll
index a2a80e04b3f2e..180985bf86159 100644
--- a/llvm/test/CodeGen/AArch64/machine_cse_illegal_hoist.ll
+++ b/llvm/test/CodeGen/AArch64/machine_cse_illegal_hoist.ll
@@ -8,7 +8,7 @@
; CHECK: adrp
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
@var = hidden local_unnamed_addr global i32 0, align 4
@_ZTIi = external dso_local constant ptr
diff --git a/llvm/test/CodeGen/AArch64/pr40091.ll b/llvm/test/CodeGen/AArch64/pr40091.ll
index b70ae8a39b7ea..e42fe047725c3 100644
--- a/llvm/test/CodeGen/AArch64/pr40091.ll
+++ b/llvm/test/CodeGen/AArch64/pr40091.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-arm-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define i64 @test(i64 %aa) {
; CHECK-LABEL: test:
diff --git a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
index 7570b8b03b884..d1d9db1035137 100644
--- a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+++ b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
@A = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
@B = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
diff --git a/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll b/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
index 1662e27ecdefd..41dae74c0bd30 100644
--- a/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll
@@ -1,4 +1,4 @@
-; RUN: llc -asm-verbose=0 -mtriple aarch64-arm-none-eabi < %s | FileCheck %s
+; RUN: llc -asm-verbose=0 -mtriple aarch64 < %s | FileCheck %s
; The following code previously broke in the DAGCombiner. Specifically, trying to combine:
; extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x
diff --git a/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll b/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
index 6a47fee824255..0f7ea36949da5 100644
--- a/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
+++ b/llvm/test/CodeGen/AArch64/strict-fp-int-promote.ll
@@ -2,7 +2,7 @@
; RUN: llc -O0 -o - %s | FileCheck %s
; RUN: llc -O3 -o - %s | FileCheck %s --check-prefix=SUBOPTIMAL
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
diff --git a/llvm/test/CodeGen/AArch64/tailcall-bitcast-memcpy.ll b/llvm/test/CodeGen/AArch64/tailcall-bitcast-memcpy.ll
index 0f337eea836c4..20ab0d52d90ff 100644
--- a/llvm/test/CodeGen/AArch64/tailcall-bitcast-memcpy.ll
+++ b/llvm/test/CodeGen/AArch64/tailcall-bitcast-memcpy.ll
@@ -1,5 +1,5 @@
;RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
;CHECK-LABEL: @wmemcpy
;CHECK: lsl
diff --git a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
index f7b90868b2826..566753b7d4d10 100644
--- a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
+++ b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
+# RUN: llc -mtriple=aarch64 -o - %s \
# RUN: -run-pass register-coalescer | FileCheck %s
# In this test case, the 32-bit copy implements a 32 to 64 bit zero extension
diff --git a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
index 1feb96a6403ad..bbb59de2737f8 100644
--- a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
@@ -1,7 +1,7 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -run-pass=prologepilog -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=prologepilog -o - %s 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
+ target triple = "aarch64"
define dso_local i32 @foo() "sign-return-address"="all" "sign-return-address-key"="a_key" {
entry:
diff --git a/llvm/test/DebugInfo/AArch64/return-address-signing.ll b/llvm/test/DebugInfo/AArch64/return-address-signing.ll
index c679a9da65d6e..0b32d001c08a0 100644
--- a/llvm/test/DebugInfo/AArch64/return-address-signing.ll
+++ b/llvm/test/DebugInfo/AArch64/return-address-signing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-arm-none-eabi < %s -filetype=obj -o - \
+; RUN: llc -mtriple=aarch64 < %s -filetype=obj -o - \
; RUN: | llvm-dwarfdump -v - | FileCheck -check-prefix=CHECK %s
;CHECK: CIE
diff --git a/llvm/test/MC/AArch64/armv9a-rme.s b/llvm/test/MC/AArch64/armv9a-rme.s
index 29ff1ab700b26..80b1d7d57a463 100644
--- a/llvm/test/MC/AArch64/armv9a-rme.s
+++ b/llvm/test/MC/AArch64/armv9a-rme.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -show-encoding %s 2> %t | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -mattr +rme -show-encoding %s 2> %t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
-// RUN: not llvm-mc -triple aarch64-arm-none-eabi -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK-NO-RME %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK-NO-RME %s
// RUN: FileCheck --check-prefix=CHECK-NO-RME-ERROR %s < %t
msr MFAR_EL3, x0
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt b/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt
index eedac19a9a51b..de7121c3b3972 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt
@@ -1,12 +1,12 @@
-# RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr=+mops,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE
+# RUN: not llvm-mc -triple aarch64 -mattr=+mops,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE
# RUN: FileCheck %s --check-prefix=CHECK-INVALID < %t
-# RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr=+v8.8a,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE
+# RUN: not llvm-mc -triple aarch64 -mattr=+v8.8a,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE
# RUN: FileCheck %s --check-prefix=CHECK-INVALID < %t
-# RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr=+mops -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS
+# RUN: not llvm-mc -triple aarch64 -mattr=+mops -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS
# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MTE < %t
-# RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr=+v8.8a -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS
+# RUN: not llvm-mc -triple aarch64 -mattr=+v8.8a -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS
# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MTE < %t
-# RUN: not llvm-mc -triple aarch64-arm-none-eabi -disassemble < %s 2> %t
+# RUN: not llvm-mc -triple aarch64 -disassemble < %s 2> %t
# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MOPS,CHECK-NO-MTE < %t
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
index c0bb1a6b76b7c..25812004be2c0 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -disassemble %s 2>&1 | FileCheck %s
-# RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-RME %s
+# RUN: llvm-mc -triple aarch64 -mattr +rme -disassemble %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple aarch64 -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-RME %s
[0xa0,0x60,0x3e,0xd5]
[0xc0,0x21,0x3e,0xd5]
diff --git a/llvm/test/MC/ELF/cfi-b-key-frame.s b/llvm/test/MC/ELF/cfi-b-key-frame.s
index 95d514674d64a..c1bd1c387949c 100644
--- a/llvm/test/MC/ELF/cfi-b-key-frame.s
+++ b/llvm/test/MC/ELF/cfi-b-key-frame.s
@@ -1,5 +1,5 @@
// REQUIRES: aarch64-registered-target
-// RUN: llvm-mc -filetype=obj -triple aarch64-arm-none-eabi %s -o - | llvm-dwarfdump - -v | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple aarch64 %s -o - | llvm-dwarfdump - -v | FileCheck %s
#CHECK: Augmentation: "zRB"
f1:
.cfi_startproc
diff --git a/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll b/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
index 61389cd640a85..362cc0f6c4493 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
@@ -2,7 +2,7 @@
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; Turning a table lookup intrinsic into a shuffle vector instruction
; can be beneficial. If the mask used for the lookup is the constant
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
index 2849c83974438..079aeb54ebd87 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
@@ -3,7 +3,7 @@
; RUN: opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S -o - < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; This test is not vectorized on AArch64 due to requiring predicated loads.
; It should also not be interleaved as the predicated interleaving will just
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/multiple_reduction.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/multiple_reduction.ll
index 7a7a6e72565f1..c9e79c84dbf8e 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/multiple_reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/multiple_reduction.ll
@@ -2,7 +2,7 @@
; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
; This test has mutual reductions, referencing the same data:
; for i = ...
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/phi-use-order-scalable.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/phi-use-order-scalable.ll
index 8e30d1865bf61..bbf6e48d0ef90 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/phi-use-order-scalable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/phi-use-order-scalable.ll
@@ -2,7 +2,7 @@
; RUN: opt -passes=slp-vectorizer -S < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
define <vscale x 8 x i32> @scalable(i1 %c, i32 %srcALen, i32 %srcBLen) {
; CHECK-LABEL: @scalable(
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