[llvm] 65de6b0 - [RISCV] Remove legacy TA/TU pseudo distinction for VID
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 09:12:25 PDT 2023
Author: Philip Reames
Date: 2023-06-27T09:12:00-07:00
New Revision: 65de6b0b0e10ee45655ad52432bfc6f98253ef6c
URL: https://github.com/llvm/llvm-project/commit/65de6b0b0e10ee45655ad52432bfc6f98253ef6c
DIFF: https://github.com/llvm/llvm-project/commit/65de6b0b0e10ee45655ad52432bfc6f98253ef6c.diff
LOG: [RISCV] Remove legacy TA/TU pseudo distinction for VID
This is a follow on to D152740. The focus of this patch is on actually removing the old TA (unsuffixed) version. I realized we already had plumbing for combined TA/TU pseudos - used by some of the ternary instructions. As such, we can go ahead and fully remove the old TA, and rename the _TU variant to be unsuffixed. (The rename must happen in this patch for the table structure to work out as expected.)
The scheduling difference comes from an omission in D152740. If we selected a _MASK variant - either from manual ISEL or instrincs - we were going through doPeepholeMaskedRVV and still getting the TA variant. The use of the IsCombined flag in the MaskedPseudo table causes us to use the TU (now unsuffixed) variant instead.
Differential Revision: https://reviews.llvm.org/D153155
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/stepvector.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 24e3929896e62..a718d19aab190 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -537,11 +537,23 @@ def RISCVVIntrinsicsTable : GenericTable {
let PrimaryKeyName = "getRISCVVIntrinsicInfo";
}
-class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true, bit IsTernary = false> {
+// Describes the relation of a masked pseudo to the unmasked variants.
+// (HasTU = true, IsCombined = false)
+// Has both a TA (unsuffixed) and _TU variant defined. TU variant
+// may (or may not) have a vector policy operand.
+// (HasTU = false, IsCombined = false)
+// No TA (unsuffixed) or _TU variants. Masked version is only pseudo
+// (HasTU = false, IsCombined = true)
+// The unsuffixed version has a merge operand; no explicit _TU variant
+// exists. The unsuffixed version has a policy operand, and can thus
+// represent all policy states.
+// (HasTU = true, IsCombined = true)
+// Invalid and unused state.
+class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true, bit IsCombined = false> {
Pseudo MaskedPseudo = !cast<Pseudo>(NAME);
Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME));
Pseudo UnmaskedTUPseudo = !cond(HasTU : !cast<Pseudo>(!subst("_MASK", "", NAME # "_TU")),
- IsTernary : UnmaskedPseudo,
+ IsCombined : UnmaskedPseudo,
true : MaskedPseudo);
bits<4> MaskOpIdx = MaskIdx;
}
@@ -977,25 +989,15 @@ class VPseudoSStoreMask<VReg StClass, int EEW>:
class VPseudoNullaryNoMask<VReg RegClass>:
Pseudo<(outs RegClass:$rd),
- (ins AVL:$vl, ixlenimm:$sew),
- []>, RISCVVPseudo {
- let mayLoad = 0;
- let mayStore = 0;
- let hasSideEffects = 0;
- let HasVLOp = 1;
- let HasSEWOp = 1;
-}
-
-class VPseudoNullaryNoMaskTU<VReg RegClass>:
- Pseudo<(outs RegClass:$rd),
- (ins RegClass:$merge, AVL:$vl, ixlenimm:$sew),
- []>, RISCVVPseudo {
+ (ins RegClass:$merge, AVL:$vl, ixlenimm:$sew,
+ ixlenimm:$policy), []>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
+ let HasVecPolicyOp = 1;
}
class VPseudoNullaryMask<VReg RegClass>:
@@ -1926,10 +1928,10 @@ multiclass VPseudoVID_V {
let VLMul = m.value in {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
- def "_V_" # m.MX # "_TU": VPseudoNullaryNoMaskTU<m.vrclass>,
- Sched<[WriteVMIdxV_MX, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 1,
+ /*HasTU=*/false,
+ /*IsCombined=*/true>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
}
}
@@ -3224,7 +3226,7 @@ multiclass VPseudoTernaryWithPolicy<VReg RetClass,
let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false, /*IsTernary*/true>;
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false, /*IsCombined*/true>;
}
}
@@ -4531,16 +4533,11 @@ multiclass VPatNullaryV<string intrinsic, string instruction>
{
foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
- (vti.Vector undef),
- VLOpFrag)),
- (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_TU")
- (vti.Vector (IMPLICIT_DEF)), GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
(vti.Vector vti.RegClass:$merge),
VLOpFrag)),
- (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_TU")
- vti.RegClass:$merge, GPR:$vl, vti.Log2SEW)>;
+ (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
+ vti.RegClass:$merge, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
(vti.Vector vti.RegClass:$merge),
(vti.Mask V0), VLOpFrag, (XLenVT timm:$policy))),
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 4e756448663ed..2d4d798f164c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -154,10 +154,10 @@ define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() {
; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 3
-; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: li a0, -3
-; CHECK-NEXT: vmadd.vx v8, a0, v9
+; CHECK-NEXT: vmacc.vx v8, a0, v9
; CHECK-NEXT: ret
ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>
}
@@ -166,10 +166,10 @@ define void @buildvec_vid_stepn3_addn3_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3)
; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, -3
-; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vmv.v.i v9, -3
; CHECK-NEXT: li a4, -3
-; CHECK-NEXT: vmadd.vx v9, a4, v8
+; CHECK-NEXT: vmacc.vx v9, a4, v8
; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: vse32.v v9, (a2)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index be32acbaff9c6..7dc7d7c49b4dc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -1444,10 +1444,10 @@ define void @mulhs_v6i16(ptr %x) {
; CHECK-NEXT: vmerge.vim v9, v9, 7, v0
; CHECK-NEXT: vdiv.vv v9, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vid.v v11
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vmv.v.i v11, 7
; CHECK-NEXT: li a1, -14
-; CHECK-NEXT: vmadd.vx v11, a1, v10
+; CHECK-NEXT: vmacc.vx v11, a1, v10
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index a4c2fa02d55bd..5f8ed48472ea7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -713,8 +713,8 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vi v8, v24, 4
+; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vi v20, v8, 4
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb
@@ -724,7 +724,7 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v24, v24, 8
+; RV64-NEXT: vslidedown.vi v24, v8, 8
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45
; RV64-NEXT: mul a1, a1, a2
@@ -732,15 +732,15 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vrgather.vi v8, v24, 2, v0.t
+; RV64-NEXT: vrgather.vi v20, v24, 2, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: vmv.v.v v20, v16
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69
@@ -822,15 +822,21 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v12, v16, v8
-; RV64-NEXT: vrgather.vi v12, v24, 4, v0.t
+; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v16, v24, v8
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 45
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vi v16, v8, 4, v0.t
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69
@@ -1174,8 +1180,15 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v16
-; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 29
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vse64.v v8, (a0)
+; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vse64.v v12, (a1)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
@@ -1201,16 +1214,9 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 64
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 25
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
-; RV64-NEXT: vse64.v v8, (a1)
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 29
+; RV64-NEXT: li a2, 25
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 2857d45242dfe..570842c2b39f8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -1796,20 +1796,20 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m,
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
-; RV32-NEXT: li a3, 32
-; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: lui a2, %hi(.LCPI72_0)
; RV32-NEXT: addi a2, a2, %lo(.LCPI72_0)
+; RV32-NEXT: li a3, 32
+; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vle32.v v16, (a2)
; RV32-NEXT: mv a2, a0
-; RV32-NEXT: vid.v v24
-; RV32-NEXT: vmsltu.vx v12, v24, a1
+; RV32-NEXT: vmsltu.vx v12, v16, a1
+; RV32-NEXT: vid.v v16
; RV32-NEXT: vmsltu.vx v13, v16, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT: vslideup.vi v12, v13, 4
+; RV32-NEXT: vslideup.vi v13, v12, 4
; RV32-NEXT: li a0, 64
; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; RV32-NEXT: vmand.mm v0, v12, v0
+; RV32-NEXT: vmand.mm v0, v13, v0
; RV32-NEXT: vmv.v.i v12, 1
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: vslidedown.vx v12, v8, a3
@@ -1839,20 +1839,20 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m,
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
-; RV64-NEXT: li a3, 32
-; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: lui a2, %hi(.LCPI72_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI72_0)
+; RV64-NEXT: li a3, 32
+; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v16, (a2)
; RV64-NEXT: mv a2, a0
-; RV64-NEXT: vid.v v24
-; RV64-NEXT: vmsltu.vx v12, v24, a1
+; RV64-NEXT: vmsltu.vx v12, v16, a1
+; RV64-NEXT: vid.v v16
; RV64-NEXT: vmsltu.vx v13, v16, a1
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vi v12, v13, 4
+; RV64-NEXT: vslideup.vi v13, v12, 4
; RV64-NEXT: li a0, 64
; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; RV64-NEXT: vmand.mm v0, v12, v0
+; RV64-NEXT: vmand.mm v0, v13, v0
; RV64-NEXT: vmv.v.i v12, 1
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: vslidedown.vx v12, v8, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
index e6b3c25b5d935..ea14e40d08751 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
@@ -139,10 +139,10 @@ define void @store_constant_v2i32(ptr %p) {
; CHECK-LABEL: store_constant_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 3
-; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: li a1, 3
-; CHECK-NEXT: vmadd.vx v9, a1, v8
+; CHECK-NEXT: vmacc.vx v9, a1, v8
; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
store <2 x i32> <i32 3, i32 6>, ptr %p
@@ -215,10 +215,10 @@ define void @store_constant_v2i8_align1(ptr %p) {
; CHECK-LABEL: store_constant_v2i8_align1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 3
-; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: li a1, 3
-; CHECK-NEXT: vmadd.vx v9, a1, v8
+; CHECK-NEXT: vmacc.vx v9, a1, v8
; CHECK-NEXT: vse8.v v9, (a0)
; CHECK-NEXT: ret
store <2 x i8> <i8 3, i8 6>, ptr %p, align 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
index 11dba172049ce..a3d4d13f3a8fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
@@ -16,11 +16,11 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
@@ -33,10 +33,10 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
@@ -48,10 +48,10 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
@@ -63,11 +63,11 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
@@ -80,10 +80,10 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
@@ -95,10 +95,10 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
@@ -114,11 +114,11 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
@@ -131,10 +131,10 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
@@ -146,10 +146,10 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
@@ -161,11 +161,11 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
@@ -178,10 +178,10 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
@@ -193,10 +193,10 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
@@ -304,11 +304,11 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
@@ -321,10 +321,10 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-256-NEXT: vand.vi v8, v12, 1
@@ -336,10 +336,10 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-512-NEXT: vand.vi v8, v12, 1
@@ -351,11 +351,11 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
@@ -368,10 +368,10 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-256-NEXT: vand.vi v8, v12, 1
@@ -383,10 +383,10 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-512-NEXT: vand.vi v8, v12, 1
@@ -402,11 +402,11 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
@@ -419,10 +419,10 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-256-NEXT: vand.vi v8, v16, 1
@@ -434,10 +434,10 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-512-NEXT: vand.vi v8, v16, 1
@@ -449,11 +449,11 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
@@ -466,10 +466,10 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-256-NEXT: vand.vi v8, v16, 1
@@ -481,10 +481,10 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-512-NEXT: vand.vi v8, v16, 1
@@ -500,11 +500,11 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16
@@ -519,10 +519,10 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV32-BITS-256-NEXT: vand.vi v8, v24, 1
@@ -534,11 +534,11 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-512-NEXT: vrgather.vv v28, v8, v16
; RV32-BITS-512-NEXT: vrgather.vv v24, v12, v16
@@ -552,11 +552,11 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16
@@ -571,10 +571,10 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV64-BITS-256-NEXT: vand.vi v8, v24, 1
@@ -586,11 +586,11 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-512-NEXT: vrgather.vv v28, v8, v16
; RV64-BITS-512-NEXT: vrgather.vv v24, v12, v16
@@ -609,11 +609,11 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -622,11 +622,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv1i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9
@@ -634,11 +634,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv1i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 3
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9
@@ -646,11 +646,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -659,11 +659,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv1i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9
@@ -671,11 +671,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv1i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 3
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9
@@ -687,11 +687,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -700,11 +700,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv2i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9
@@ -712,11 +712,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv2i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9
@@ -724,11 +724,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -737,11 +737,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv2i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9
@@ -749,11 +749,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv2i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9
@@ -765,11 +765,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -778,11 +778,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv4i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9
@@ -790,11 +790,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv4i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9
@@ -802,11 +802,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
@@ -815,11 +815,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv4i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9
@@ -827,11 +827,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv4i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9
@@ -915,11 +915,11 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
@@ -928,11 +928,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv16i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v12
; RV32-BITS-256-NEXT: vmv.v.v v8, v10
@@ -940,11 +940,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv16i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v12
; RV32-BITS-512-NEXT: vmv.v.v v8, v10
@@ -952,11 +952,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
@@ -965,11 +965,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv16i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v12
; RV64-BITS-256-NEXT: vmv.v.v v8, v10
@@ -977,11 +977,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv16i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12
; RV64-BITS-512-NEXT: vmv.v.v v8, v10
@@ -993,11 +993,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
@@ -1006,11 +1006,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv32i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0
; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v16
; RV32-BITS-256-NEXT: vmv.v.v v8, v12
@@ -1018,11 +1018,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv32i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0
; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v16
; RV32-BITS-512-NEXT: vmv.v.v v8, v12
@@ -1030,11 +1030,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
@@ -1043,11 +1043,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv32i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0
; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v16
; RV64-BITS-256-NEXT: vmv.v.v v8, v12
@@ -1055,11 +1055,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv32i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0
; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16
; RV64-BITS-512-NEXT: vmv.v.v v8, v12
@@ -1071,11 +1071,11 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i8:
; RV32-BITS-UNKNOWN: # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24
@@ -1085,11 +1085,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
;
; RV32-BITS-256-LABEL: reverse_nxv64i8:
; RV32-BITS-256: # %bb.0:
+; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1
-; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v24
; RV32-BITS-256-NEXT: vmv.v.v v8, v16
@@ -1097,11 +1097,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
;
; RV32-BITS-512-LABEL: reverse_nxv64i8:
; RV32-BITS-512: # %bb.0:
+; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
-; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v24
; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v24
@@ -1110,11 +1110,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i8:
; RV64-BITS-UNKNOWN: # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
-; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24
@@ -1124,11 +1124,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
;
; RV64-BITS-256-LABEL: reverse_nxv64i8:
; RV64-BITS-256: # %bb.0:
+; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1
-; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v24
; RV64-BITS-256-NEXT: vmv.v.v v8, v16
@@ -1136,11 +1136,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
;
; RV64-BITS-512-LABEL: reverse_nxv64i8:
; RV64-BITS-512: # %bb.0:
+; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
-; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v24
; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24
@@ -1153,11 +1153,11 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) {
; CHECK-LABEL: reverse_nxv1i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1169,11 +1169,11 @@ define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) {
define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) {
; CHECK-LABEL: reverse_nxv2i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1185,11 +1185,11 @@ define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) {
define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) {
; CHECK-LABEL: reverse_nxv4i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1216,11 +1216,11 @@ define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) {
define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) {
; CHECK-LABEL: reverse_nxv16i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
@@ -1232,11 +1232,11 @@ define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) {
define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) {
; CHECK-LABEL: reverse_nxv32i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16
@@ -1248,11 +1248,11 @@ define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) {
define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) {
; CHECK-LABEL: reverse_nxv1i32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1264,11 +1264,11 @@ define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) {
define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) {
; CHECK-LABEL: reverse_nxv2i32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1280,11 +1280,11 @@ define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) {
define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) {
; CHECK-LABEL: reverse_nxv4i32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
@@ -1311,11 +1311,11 @@ define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) {
define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) {
; CHECK-LABEL: reverse_nxv16i32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16
@@ -1327,11 +1327,11 @@ define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) {
define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) {
; CHECK-LABEL: reverse_nxv1i64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1343,11 +1343,11 @@ define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) {
define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-LABEL: reverse_nxv2i64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
@@ -1359,11 +1359,11 @@ define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {
define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) {
; CHECK-LABEL: reverse_nxv4i64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
@@ -1394,11 +1394,11 @@ define <vscale x 8 x i64> @reverse_nxv8i64(<vscale x 8 x i64> %a) {
define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) {
; CHECK-LABEL: reverse_nxv1f16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1410,11 +1410,11 @@ define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) {
define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) {
; CHECK-LABEL: reverse_nxv2f16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1426,11 +1426,11 @@ define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) {
define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) {
; CHECK-LABEL: reverse_nxv4f16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1457,11 +1457,11 @@ define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) {
define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) {
; CHECK-LABEL: reverse_nxv16f16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
@@ -1473,11 +1473,11 @@ define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) {
define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) {
; CHECK-LABEL: reverse_nxv32f16:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16
@@ -1489,11 +1489,11 @@ define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) {
define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) {
; CHECK-LABEL: reverse_nxv1f32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
@@ -1505,11 +1505,11 @@ define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) {
define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) {
; CHECK-LABEL: reverse_nxv2f32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1521,11 +1521,11 @@ define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) {
define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) {
; CHECK-LABEL: reverse_nxv4f32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
@@ -1552,11 +1552,11 @@ define <vscale x 8 x float> @reverse_nxv8f32(<vscale x 8 x float> %a) {
define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) {
; CHECK-LABEL: reverse_nxv16f32:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16
@@ -1568,11 +1568,11 @@ define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) {
define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) {
; CHECK-LABEL: reverse_nxv1f64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9
@@ -1584,11 +1584,11 @@ define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) {
define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {
; CHECK-LABEL: reverse_nxv2f64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
@@ -1600,11 +1600,11 @@ define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {
define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) {
; CHECK-LABEL: reverse_nxv4f64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
@@ -1633,11 +1633,11 @@ define <vscale x 8 x double> @reverse_nxv8f64(<vscale x 8 x double> %a) {
define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) {
; CHECK-LABEL: reverse_nxv3i64:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v12, v12, a0
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv1r.v v8, v17
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
index 9f5c1c97ddc67..30ec0899da8e4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
@@ -341,10 +341,10 @@ define <8 x i32> @v4i32_2(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 7
; CHECK-NEXT: vrgather.vv v10, v8, v16
-; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -501,9 +501,10 @@ define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) {
; RV32-NEXT: vrsub.vi v19, v18, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV32-NEXT: vrsub.vi v8, v18, 3
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 15
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vrsub.vi v8, v18, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
@@ -516,10 +517,10 @@ define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) {
; RV64-NEXT: vid.v v20
; RV64-NEXT: vrsub.vi v24, v20, 7
; RV64-NEXT: vrgather.vv v12, v8, v24
-; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
@@ -692,10 +693,10 @@ define <8 x float> @v4f32_2(<4 x float> %a, <4 x float> %b) {
; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 7
; CHECK-NEXT: vrgather.vv v10, v8, v16
-; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -795,9 +796,10 @@ define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) {
; RV32-NEXT: vrsub.vi v19, v18, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV32-NEXT: vrsub.vi v8, v18, 3
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 15
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vrsub.vi v8, v18, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
@@ -810,10 +812,10 @@ define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) {
; RV64-NEXT: vid.v v20
; RV64-NEXT: vrsub.vi v24, v20, 7
; RV64-NEXT: vrgather.vv v12, v8, v24
-; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
index 9ab68be45616e..e20783d1a43ec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
@@ -501,8 +501,8 @@ define <vscale x 8 x i64> @mul_bigimm_stepvector_nxv8i64() {
; RV32-NEXT: lui a0, 797989
; RV32-NEXT: addi a0, a0, -683
; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: vid.v v16
; RV32-NEXT: vmul.vv v8, v16, v8
@@ -552,8 +552,8 @@ define <vscale x 16 x i64> @stepvector_nxv16i64() {
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v16, v8, v16
@@ -562,9 +562,9 @@ define <vscale x 16 x i64> @stepvector_nxv16i64() {
;
; RV64-LABEL: stepvector_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
+; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
@@ -667,8 +667,8 @@ define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() {
; RV32-NEXT: mulhu a0, a0, a2
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: sw a0, 12(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
index f3dbe3a188733..d29b6306f581a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
@@ -507,8 +507,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+ ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 -1, 6 /* e64 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}}
@@ -543,7 +544,8 @@ body: |
%0:gpr = COPY $x11
%1:gpr = COPY $x10
%2:gpr = IMPLICIT_DEF
- %3:vr = PseudoVID_V_MF2 -1, 6
+ %pt:vr = IMPLICIT_DEF
+ %3:vr = PseudoVID_V_MF2 %pt, -1, 6, 0
%4:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5
bb.1:
@@ -593,8 +595,9 @@ body: |
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -617,7 +620,8 @@ body: |
%1:gpr = PseudoReadVLENB
%2:gpr = SRLI %1:gpr, 3
%3:gpr = COPY $x11
- %4:vr = PseudoVID_V_M1 -1, 6
+ %pt:vr = IMPLICIT_DEF
+ %4:vr = PseudoVID_V_M1 %pt, -1, 6, 0
%5:gpr = COPY $x0
bb.1:
@@ -661,8 +665,9 @@ body: |
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -689,7 +694,8 @@ body: |
%1:gpr = PseudoReadVLENB
%2:gpr = SRLI %1:gpr, 3
%3:gpr = COPY $x11
- %4:vr = PseudoVID_V_M1 -1, 6
+ %pt:vr = IMPLICIT_DEF
+ %4:vr = PseudoVID_V_M1 %pt, -1, 6, 3
%5:gpr = COPY $x0
bb.1:
@@ -919,15 +925,16 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
+ ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %11, %bb.3
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %12, %bb.3
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[PHI]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], killed [[ADD]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
@@ -968,7 +975,8 @@ body: |
%12:gpr = COPY $x15
%vlenb:gpr = PseudoReadVLENB
%inc:gpr = SRLI killed %vlenb, 3
- %10:vr = PseudoVID_V_M1 -1, 6
+ %pt:vr = IMPLICIT_DEF
+ %10:vr = PseudoVID_V_M1 %pt, -1, 6, 0
%59:gpr = COPY $x0
PseudoBR %bb.1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 2298a2ec710c7..247b83581c3e3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -419,12 +419,14 @@ body: |
; CHECK-LABEL: name: vmv_v_i_
diff erent_lmuls
; CHECK: liveins: $x10, $v8, $x11
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 4, 6 /* e64 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 0, 4, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET
- %0:vrm2 = PseudoVID_V_M2 4, 6
+ %pt:vrm2 = IMPLICIT_DEF
+ %0:vrm2 = PseudoVID_V_M2 %pt, 4, 6, 3
%4:vr = PseudoVMV_V_I_MF4 0, 4, 3
PseudoRET
...
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