[PATCH] D153316: [AArch64][SelectionDAG] fix infinite loop caused by legalizing & combining CONCAT_VECTORS

[FLZ via Phabricator via llvm-commits]

FLZ101 updated this revision to Diff 534411.
FLZ101 added a comment.

Fix a format issue


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153316/new/

https://reviews.llvm.org/D153316

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll


Index: llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+
+; just need to check whether commands above could exit normally rather than get stuck in an
+; infinite loop as described in https://github.com/llvm/llvm-project/issues/63322 and end with
+; a stack dump
+;
+; CHECK-LABEL: allocno_reload_assign:
+
+declare void @llvm.masked.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8>, <vscale x 16 x ptr>, i32 immarg, <vscale x 16 x i1>)
+
+define fastcc i8 @allocno_reload_assign() {
+  br label %1
+
+1:                                                ; preds = %1, %0
+  call void @llvm.masked.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x ptr> zeroinitializer, i32 0, <vscale x 16 x i1> xor (<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> icmp eq (<vscale x 16 x ptr> insertelement (<vscale x 16 x ptr> poison, ptr null, i64 0), <vscale x 16 x ptr> zeroinitializer), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer), <vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i32 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)))
+  br label %1
+}
+
+uselistorder <vscale x 16 x i1> poison, { 1, 2, 0 }
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23167,7 +23167,14 @@
 
     // If the input is a concat_vectors, just make a larger concat by padding
     // with smaller undefs.
-    if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) {
+    //
+    // Legalizing in AArch64TargetLowering::LowerCONCAT_VECTORS() and combining
+    // here could cause an infinite loop. That legalizing happens when LegalDAG
+    // is true and input of AArch64TargetLowering::LowerCONCAT_VECTORS() is
+    // scalable. To avoid the infinite loop, we skip combining here when
+    // LegalDAG is true and the combining would produce a scalable vector.
+    if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
+        !(LegalDAG && In.getValueType().isScalableVector())) {
       unsigned NumOps = N->getNumOperands() * In.getNumOperands();
       SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
       Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType()));


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