[PATCH] D153666: [RISCV] Add GPR bypasses for most integer instructions to the SiFive7 scheduler model.

[Craig Topper via Phabricator via llvm-commits]

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SiFive7's scalar execution consists of 4 stages AG, M1 <https://reviews.llvm.org/M1>, M2 <https://reviews.llvm.org/M2>, WB.
Most simple arithmetic and branch instructions can execute in
either AG or M2 <https://reviews.llvm.org/M2>.

If the operands are ready, the instruction will execute in the AG
stage. Otherwise, it executes in the M2 <https://reviews.llvm.org/M2> stage. Everything is fully
bypassed, so dependent instructions should only see 1 cycle latency.

This patch adds ReadAdvances to pretend that these instructions
execute in the M2 <https://reviews.llvm.org/M2> ALU and reads their operands then. This allows
the scheduler to schedule dependent instructions back to back.

I've increased branch latency to 3 since they are also executed in both
stages. Still need to fix JALR, but I want to cleanup some scheduler
classes first.

Multiply, cpop and division instructions can only start in the AG stage.

Still need to do some work for FP instructions that produce integer results.

I've added an llvm-mca test that creates a long dependency chain.
The timeline view can show that things are bypassed. I
didn't check all permutations, but we have some variety.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153666

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
  llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s

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