[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

[garvit gupta via Phabricator via llvm-commits]

garvitgupta08 updated this revision to Diff 533668.
garvitgupta08 added a comment.

Addressed the comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

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