[llvm] 4a69fd6 - [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG)

[Weining Lu via llvm-commits]

Author: Weining Lu
Date: 2023-06-17T10:49:17+08:00
New Revision: 4a69fd62699e9cb3d80d83796826a1f5e2a9ef9e

URL: https://github.com/llvm/llvm-project/commit/4a69fd62699e9cb3d80d83796826a1f5e2a9ef9e
DIFF: https://github.com/llvm/llvm-project/commit/4a69fd62699e9cb3d80d83796826a1f5e2a9ef9e.diff

LOG: [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG)

Reviewed By: xry111

Differential Revision: https://reviews.llvm.org/D153119

Added: 
    

Modified: 
    llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
    llvm/test/CodeGen/LoongArch/intrinsic.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/LoongArch/intrinsic-la64.ll b/llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
index 7b28682b5aa97..ceb3213ea94ee 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -121,6 +121,17 @@ entry:
   ret i64 %0
 }
 
+;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
+;; FIXME: currently csrwr is not emitted.
+define void @csrwr_d_noret(i64 %a) {
+; CHECK-LABEL: csrwr_d_noret:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
+  ret void
+}
+
 define i64 @csrxchg_d(i64 %a, i64 %b) {
 ; CHECK-LABEL: csrxchg_d:
 ; CHECK:       # %bb.0: # %entry
@@ -131,6 +142,17 @@ entry:
   ret i64 %0
 }
 
+;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
+;; FIXME: currently csrxchg is not emitted.
+define void @csrxchg_d_noret(i64 %a, i64 %b) {
+; CHECK-LABEL: csrxchg_d_noret:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
+  ret void
+}
+
 define i64 @iocsrrd_d(i32 %a) {
 ; CHECK-LABEL: iocsrrd_d:
 ; CHECK:       # %bb.0: # %entry

diff  --git a/llvm/test/CodeGen/LoongArch/intrinsic.ll b/llvm/test/CodeGen/LoongArch/intrinsic.ll
index cfd54e17d1d4c..8d7c0946011f9 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -99,6 +99,17 @@ entry:
   ret i32 %0
 }
 
+;; Check that csrwr is emitted even if the return value of the intrinsic is not used.
+;; FIXME: currently csrwr is not emitted.
+define void @csrwr_w_noret(i32 signext %a) {
+; CHECK-LABEL: csrwr_w_noret:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
+  ret void
+}
+
 define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: csrxchg_w:
 ; CHECK:       # %bb.0: # %entry
@@ -109,6 +120,17 @@ entry:
   ret i32 %0
 }
 
+;; Check that csrxchg is emitted even if the return value of the intrinsic is not used.
+;; FIXME: currently csrxchg is not emitted.
+define void @csrxchg_w_noret(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: csrxchg_w_noret:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
 define i32 @iocsrrd_b(i32 %a) {
 ; CHECK-LABEL: iocsrrd_b:
 ; CHECK:       # %bb.0: # %entry