[llvm] 2ef56d1 - [RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2023-06-16T12:15:06-07:00
New Revision: 2ef56d16adbe888a7e8c20684aa98d3f07c0eb98

URL: https://github.com/llvm/llvm-project/commit/2ef56d16adbe888a7e8c20684aa98d3f07c0eb98
DIFF: https://github.com/llvm/llvm-project/commit/2ef56d16adbe888a7e8c20684aa98d3f07c0eb98.diff

LOG: [RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation

If `evaluateAsAbsolute(Value, Layout.getAssembler())` returns true, we
know the address delta is a constant and can suppress relocations
(usually SET6/SUB6).

While here, replace one evaluateKnownAbsolute call (subtle for Mach-O
workarounds; avoid if possible) with evaluateAsAbsolute.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
    llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
    llvm/test/MC/ELF/RISCV/gen-dwarf.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 68dfb6852631c..81542b2697d5f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -273,14 +273,15 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
 bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,
                                     MCAsmLayout &Layout,
                                     bool &WasRelaxed) const {
-
   const MCExpr &AddrDelta = DF.getAddrDelta();
   SmallVectorImpl<char> &Data = DF.getContents();
   SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
   size_t OldSize = Data.size();
 
   int64_t Value;
-  bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
+  if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler()))
+    return false;
+  bool IsAbsolute = AddrDelta.evaluateAsAbsolute(Value, Layout);
   assert(IsAbsolute && "CFA with invalid expression");
   (void)IsAbsolute;
 

diff  --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
index 557986fa38b56..280da01567a2b 100644
--- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
+++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
@@ -7,15 +7,29 @@
 ; RELAX-NEXT:   0x1C R_RISCV_32_PCREL - 0x0
 ; RELAX-NEXT:   0x20 R_RISCV_ADD32 - 0x0
 ; RELAX-NEXT:   0x20 R_RISCV_SUB32 - 0x0
-; RELAX-NOT:  }
-; RELAX:        0x39 R_RISCV_SET6 - 0x0
-; RELAX-NEXT:   0x39 R_RISCV_SUB6 - 0x0
-;
+; RELAX-NEXT:   0x30 R_RISCV_32_PCREL - 0x0
+; RELAX-NEXT:   0x34 R_RISCV_ADD32 - 0x0
+; RELAX-NEXT:   0x34 R_RISCV_SUB32 - 0x0
+; RELAX-NEXT:   0x44 R_RISCV_32_PCREL - 0x0
+; RELAX-NEXT:   0x48 R_RISCV_ADD32 - 0x0
+; RELAX-NEXT:   0x48 R_RISCV_SUB32 - 0x0
+; RELAX-NEXT:  }
+
 ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation
-; RELAX-DWARFDUMP: CIE
-; RELAX-DWARFDUMP: DW_CFA_advance_loc
-; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset
-; RELAX-DWARFDUMP: DW_CFA_offset
+; RELAX-DWARFDUMP:      FDE
+; RELAX-DWARFDUMP-NEXT: Format:
+; RELAX-DWARFDUMP:      DW_CFA_advance_loc: 4
+; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16
+; RELAX-DWARFDUMP-EMPTY:
+
+; RELAX-DWARFDUMP:      FDE
+; RELAX-DWARFDUMP:      Format:
+; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4
+; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16
+; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4
+; RELAX-DWARFDUMP-NEXT: DW_CFA_offset: X1 -4
+; RELAX-DWARFDUMP-NEXT: DW_CFA_nop
+; RELAX-DWARFDUMP-EMPTY:
 source_filename = "frame.c"
 
 ; Function Attrs: noinline nounwind optnone

diff  --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s
index a9e9d2c730bbb..c0c8cae61c72b 100644
--- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s
+++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s
@@ -45,8 +45,6 @@
 # RELOC-NEXT:   0x20 R_RISCV_SUB32 - 0x0
 # RELOC-NEXT:   0x25 R_RISCV_SET6 - 0x0
 # RELOC-NEXT:   0x25 R_RISCV_SUB6 - 0x0
-# RELOC-NEXT:   0x28 R_RISCV_SET6 - 0x0
-# RELOC-NEXT:   0x28 R_RISCV_SUB6 - 0x0
 # RELOC-NEXT:   0x34 R_RISCV_32_PCREL - 0x0
 # RELOC-NEXT:   0x38 R_RISCV_ADD32 - 0x0
 # RELOC-NEXT:   0x38 R_RISCV_SUB32 - 0x0